Forums
New posts
Search forums
Members
Current visitors
Log in
Register
What's new
Search
Search
Search titles only
By:
New posts
Search forums
Menu
Log in
Register
Install the app
Install
Forums
Archive
Archive
VHDL
how to write text in vhdl
JavaScript is disabled. For a better experience, please enable JavaScript in your browser before proceeding.
Reply to thread
Message
[QUOTE="Andy, post: 3393717"] If the std_logic_vector does not contain meta values, you can use something like integer'image(to_integer(unsigned(p))). Unfortunately, the output would be in decimal (which could be handy at times!), not binary/hex. Andy [/QUOTE]
Verification
Post reply
Forums
Archive
Archive
VHDL
how to write text in vhdl
Top