I can use std_logic_vector only as input signal in Xilinx?

[Will]

Hi all,

When I assign an input signal as integer or real, I can only change
its value as a bit in test bench using Xilinx ISE 9.2i. Is
std_logic_vector the only right type for an input signal to input an
integer?

Thanks and bow.

 

[joris]

A entity "should" have std_logic/std_logic_vector input/outputs only (this is required byt Xilinx ISE anyway)

You can use integer-type or other types in the test bench, as long as you convert them to/from std_logic_vector for inputs/outputs of the component that's being tested.