Implementation Problem.

[tcl]

I'm doing a research about 3DES in C programming and VHDL language. I
would like to have the same output in both language but not successful.
The source code for C language was found in the web:-
http://patux.glo.org.mx/crypto_programs/sim/3des/des.c.html

And the VHDL code that I implement as below:-
entity tdes is
port (
d : in std_logic_vector(1 to 64);
key1 : in std_logic_vector(1 to 64);
key2 : in std_logic_vector(1 to 64);
key3 : in std_logic_vector(1 to 64);
first : in std_logic;
do_next : in std_logic;
crypt : in std_logic;
clk : in std_logic;
nreset : in std_logic;
q : out std_logic_vector(1 to 64);
done : out std_logic
);
end;

architecture simple of tdes is

component core
port (
key : in std_logic_vector(1 to 64);
d : in std_logic_vector(1 to 64);
start : in std_logic;
crypt : in std_logic;
clk : in std_logic;
nreset: in std_logic;
q : out std_logic_vector(1 to 64);
done : out std_logic
);
end component;

signal des_key : std_logic_vector(1 to 64);
signal des_d : std_logic_vector(1 to 64);
signal des_start : std_logic;
signal des_crypt : std_logic;
signal des_q : std_logic_vector(1 to 64);
signal des_done : std_logic;
signal next_dreg : std_logic_vector(1 to 64);
signal dreg : std_logic_vector(1 to 64);
signal dreg2 : std_logic_vector(1 to 64);
signal int_q : std_logic_vector(1 to 64);
signal ivsel : std_logic_vector(1 to 64);
signal next_state : std_logic_vector(0 to 1);
signal state : std_logic_vector(0 to 1);
signal ff_des_done : std_logic;
signal int_done : std_logic;
signal ff_crypt : std_logic;
signal next_int_done : std_logic;

begin

i_des : core
port map (
key => des_key,
d => des_d,
start => des_start,
crypt => des_crypt,
clk => clk,
nreset=> nreset,
q => des_q,
done => des_done
);
----------------------------------------------------------------

ivsel <= d when (first='1' and do_next='1') else dreg2;
des_d <= ivsel when (next_state="00") else des_q;
next_dreg <= d when (do_next='1') else dreg;
des_key <= key1 when (state="00") else
key2 when (state="01") else
key3;
des_crypt <= '0' when (next_state="01") else '1';
dreg2 <= int_q when (ff_crypt='1') else dreg;
int_q <= des_q;
q <= int_q;
done <= int_done;
-- ------------------------------------------------------------
P3 : process(state,do_next,des_done,ff_des_done, int_done)
begin
if (do_next='1') then
next_int_done <= '0';
else
if ((des_done='1') AND (ff_des_done='0')) then
if ((state="10") OR (state="11")) then
next_int_done <= '1';
else
next_int_done <= '0';
end if;
else
next_int_done <= int_done;
end if;
end if;
end process;

P4 : process(state,do_next,des_done,ff_des_done)
begin
if (do_next='1') then
next_state <= "00";
des_start <= '1';
else
if ((des_done='1') AND (ff_des_done='0')) then
if ((state="10") OR (state="11")) then
next_state <= state;
des_start <= '0';
else
next_state <= state + "1";
des_start <= '1';
end if;
else
next_state <= state;
des_start <= '0';
end if;
end if;
end process;
------------------------------------------------------------
--------------------------- REGISTERS ---------
-------------------------------------------------------------
P40 : process(clk, nreset)
begin
if (nreset='0') then
dreg <= (others => '0');
state <= (others => '0');
ff_des_done <= '0';
int_done <= '0';
ff_crypt <= '0';
else
if (clk='1' and clk'event) then
dreg <= next_dreg;
state <= next_state;
ff_crypt <= crypt;
ff_des_done <= des_done;
int_done <= next_int_done;
end if;
end if;
end process;

end simple;

core.vhd:-
----------------
entity core is
port (
key : in std_logic_vector(1 to 64);
d : in std_logic_vector(1 to 64);
start : in std_logic;
crypt : in std_logic;
clk : in std_logic;
nreset: in std_logic;
q : out std_logic_vector(1 to 64);
done : out std_logic
);
end;

---------- Architecture core --------------------
architecture simple of CORE is
component subkey
port (
key : in std_logic_vector(1 to 64);
sel : in std_logic_vector(0 to 3);
subkey : out std_logic_vector(1 to 48)
);
end component;

component subs_1
port (
entree : in std_logic_vector(0 to 5);
sortie : out std_logic_vector(0 to 3)
);
end component;

signal s_out_1 : std_logic_vector(0 to 3);
signal s_in_1 : std_logic_vector(0 to 5);

component subs_2
port (
entree : in std_logic_vector(0 to 5);
sortie : out std_logic_vector(0 to 3)
);
end component;

signal s_out_2 : std_logic_vector(0 to 3);
signal s_in_2 : std_logic_vector(0 to 5);

component subs_3
port (
entree : in std_logic_vector(0 to 5);
sortie : out std_logic_vector(0 to 3)
);
end component;

signal s_out_3 : std_logic_vector(0 to 3);
signal s_in_3 : std_logic_vector(0 to 5);

component subs_4
port (
entree : in std_logic_vector(0 to 5);
sortie : out std_logic_vector(0 to 3)
);
end component;

signal s_out_4 : std_logic_vector(0 to 3);
signal s_in_4 : std_logic_vector(0 to 5);

component subs_5
port (
entree : in std_logic_vector(0 to 5);
sortie : out std_logic_vector(0 to 3)
);
end component;

signal s_out_5 : std_logic_vector(0 to 3);
signal s_in_5 : std_logic_vector(0 to 5);

component subs_6
port (
entree : in std_logic_vector(0 to 5);
sortie : out std_logic_vector(0 to 3)
);
end component;

signal s_out_6 : std_logic_vector(0 to 3);
signal s_in_6 : std_logic_vector(0 to 5);

component subs_7
port (
entree : in std_logic_vector(0 to 5);
sortie : out std_logic_vector(0 to 3)
);
end component;

signal s_out_7 : std_logic_vector(0 to 3);
signal s_in_7 : std_logic_vector(0 to 5);

component subs_8
port (
entree : in std_logic_vector(0 to 5);
sortie : out std_logic_vector(0 to 3)
);
end component;

signal s_out_8 : std_logic_vector(0 to 3);
signal s_in_8 : std_logic_vector(0 to 5);

signal xorkey : std_logic_vector(1 to 48);
signal w : std_logic_vector(1 to 32);
signal t : std_logic_vector(1 to 32);
signal kkey : std_logic_vector(1 to 48);
signal erkey : std_logic_vector(1 to 48);
signal rkey : std_logic_vector(1 to 32);
signal lkey : std_logic_vector(1 to 32);
signal r0 : std_logic_vector(1 to 32);
signal l0 : std_logic_vector(1 to 32);
signal state : std_logic_vector(0 to 3);
signal next_state : std_logic_vector(0 to 3);
signal rkeyreg : std_logic_vector(1 to 32);
signal next_rkeyreg : std_logic_vector(1 to 32);
signal pnewbkey : std_logic_vector(1 to 32);
signal rkey_in : std_logic_vector(1 to 32);
signal lkeyreg : std_logic_vector(1 to 32);
signal next_lkeyreg : std_logic_vector(1 to 32);
signal k : std_logic_vector(1 to 64);
signal datainreg : std_logic_vector(1 to 64);
signal id : std_logic_vector(1 to 64);
signal keysel : std_logic_vector(0 to 3);
signal start_prev : std_logic;
signal ff_crypt : std_logic;
signal next_ff_crypt: std_logic;

begin

P14 : process(state,ff_crypt)
begin
if (ff_crypt='1') then
keysel <= state;
else
keysel <= not state;
end if;
end process;

i_subkey : subkey
port map (key => key, sel => keysel,subkey => kkey );

id <= datainreg;

l0<=id(58)&id(50)&id(42)&id(34)&id(26)&id(18)&id(10)&id(2)
&id(60)&id(52)&id(44)&id(36)&id(28)&id(20)&id(12)&id(4)
&id(62)&id(54)&id(46)&id(38)&id(30)&id(22)&id(14)&id(6)
&id(64)&id(56)&id(48)&id(40)&id(32)&id(24)&id(16)&id(8);

r0<=id(57)&id(49)&id(41)&id(33)&id(25)&id(17)&id(9)&id(1)
&id(59)&id(51)&id(43)&id(35)&id(27)&id(19)&id(11)&id(3)
&id(61)&id(53)&id(45)&id(37)&id(29)&id(21)&id(13)&id(5)
&id(63)&id(55)&id(47)&id(39)&id(31)&id(23)&id(15)&id(7);

P17 : process(state,r0,rkeyreg,l0,lkeyreg)
begin
if (state="0000") then
rkey_in <= r0;
lkey <= l0;
else
rkey_in <= rkeyreg;
lkey <= lkeyreg;
end if;
end process;

t <= rkey_in;

erkey<=t(32)&t(1)&t(2)&t(3)&t(4)&t(5)&t(4)&t(5)&t(6)&t(7)&t(8)&t(9)
&t(8)&t(9)&t(10)&t(11)&t(12)&t(13)&t(12)&t(13)&t(14)&t(15)&t(16)&t(17)
&t(16)&t(17)&t(18)&t(19)&t(20)&t(21)&t(20)&t(21)&t(22)&t(23)&t(24)&t(25)
&t(24)&t(25)&t(26)&t(27)&t(28)&t(29)&t(28)&t(29)&t(30)&t(31)&t(32)&t(1);

xorkey <= erkey xor kkey;
s_in_1 <= xorkey(1 to 6);
s_in_2 <= xorkey(7 to 12);
s_in_3 <= xorkey(13 to 18);
s_in_4 <= xorkey(19 to 24);
s_in_5 <= xorkey(25 to 30);
s_in_6 <= xorkey(31 to 36);
s_in_7 <= xorkey(37 to 42);
s_in_8 <= xorkey(43 to 48);

i_subs_1 : subs_1
port map (entree => s_in_1, sortie => s_out_1);

i_subs_2 : subs_2
port map (entree => s_in_2, sortie => s_out_2);

i_subs_3 : subs_3
port map (entree => s_in_3, sortie => s_out_3);

i_subs_4 : subs_4
port map (entree => s_in_4, sortie => s_out_4);

i_subs_5 : subs_5
port map (entree => s_in_5, sortie => s_out_5);

i_subs_6 : subs_6
port map (entree => s_in_6, sortie => s_out_6);

i_subs_7 : subs_7
port map (entree => s_in_7, sortie => s_out_7);

i_subs_8 : subs_8
port map (entree => s_in_8, sortie => s_out_8);


w<=s_out_1&s_out_2&s_out_3&s_out_4&s_out_5&s_out_6&s_out_7&s_out_8;

pnewbkey<=w(16)&w(7)&w(20)&w(21)&w(29)&w(12)&w(28)&w(17)
&w(1)&w(15)&w(23)&w(26)&w(5)&w(18)&w(31)&w(10)
&w(2)&w(8)&w(24)&w(14)&w(32)&w(27)&w(3)&w(9)
&w(19)&w(13)&w(30)&w(6)&w(22)&w(11)&w(4)&w(25);

rkey <= pnewbkey xor lkey;
k <= rkey & rkeyreg;

q<=k(40)&k(8)&k(48)&k(16)&k(56)&k(24)&k(64)&k(32)
&k(39)&k(7)&k(47)&k(15)&k(55)&k(23)&k(63)&k(31)
&k(38)&k(6)&k(46)&k(14)&k(54)&k(22)&k(62)&k(30)
&k(37)&k(5)&k(45)&k(13)&k(53)&k(21)&k(61)&k(29)
&k(36)&k(4)&k(44)&k(12)&k(52)&k(20)&k(60)&k(28)
&k(35)&k(3)&k(43)&k(11)&k(51)&k(19)&k(59)&k(27)
&k(34)&k(2)&k(42)&k(10)&k(50)&k(18)&k(58)&k(26)
&k(33)&k(1)&k(41)&k(9)&k(49)&k(17)&k(57)&k(25);

P27 : process(start,start_prev,state)
begin
if ((start='1') AND (start_prev='0')) then
next_state <= "0000";
else
if (state="1111") then
next_state <= "1111";
else
next_state <= state + "1";
end if;
end if;
end process;

P27_2 : process(start,crypt,ff_crypt,start_prev)
begin
if ((start='1') AND (start_prev='0')) then
next_ff_crypt <= crypt;
else
next_ff_crypt <= ff_crypt;
end if;
end process;

P28 : process(rkeyreg,lkeyreg,state,rkey,rkey_in)
begin
if (state="1111") then
next_rkeyreg <= rkeyreg;
next_lkeyreg <= lkeyreg;
done <= '1';
else
next_rkeyreg <= rkey;
next_lkeyreg <= rkey_in;
done <= '0';
end if;
end process;
-------------------------------------------------------------
--------------------------- MEMORIES ------------
-------------------------------------------------------------
P29 : process(clk, nreset)
begin
if (nreset='0') then
state <= (others => '0');
rkeyreg <= (others => '0');
lkeyreg <= (others => '0');
start_prev <= '0';
datainreg <= (others => '0');
ff_crypt <= '0';
else
if (clk='1' and clk'event) then
state <= next_state;
rkeyreg <= next_rkeyreg;
lkeyreg <= next_lkeyreg;
start_prev <= start;
datainreg <= d;
ff_crypt <= next_ff_crypt;
end if;
end if;
end process;

end simple;

subkey.vhd:-
--------------------
entity subkey is
port (
key : in std_logic_vector(1 to 64); sel : in
std_logic_vector(0 to 3);
subkey : out std_logic_vector(1 to 48)
);
end;
---------- Architecture subkey ----------
architecture simple of subkey is
signal kkey_1 : std_logic_vector(1 to 48);
signal kkey_2 : std_logic_vector(1 to 48);
signal kkey_3 : std_logic_vector(1 to 48);
signal kkey_4 : std_logic_vector(1 to 48);
signal kkey_5 : std_logic_vector(1 to 48);
signal kkey_6 : std_logic_vector(1 to 48);
signal kkey_7 : std_logic_vector(1 to 48);
signal kkey_8 : std_logic_vector(1 to 48);
signal kkey_9 : std_logic_vector(1 to 48);
signal kkey_10 : std_logic_vector(1 to 48);
signal kkey_11 : std_logic_vector(1 to 48);
signal kkey_12 : std_logic_vector(1 to 48);
signal kkey_13 : std_logic_vector(1 to 48);
signal kkey_14 : std_logic_vector(1 to 48);
signal kkey_15 : std_logic_vector(1 to 48);
signal kkey_16 : std_logic_vector(1 to 48);
signal s0_0 : std_logic_vector(1 to 48);
signal s0_1 : std_logic_vector(1 to 48);
signal s0_2 : std_logic_vector(1 to 48);
signal s0_3 : std_logic_vector(1 to 48);
signal s0_4 : std_logic_vector(1 to 48);
signal s0_5 : std_logic_vector(1 to 48);
signal s0_6 : std_logic_vector(1 to 48);
signal s0_7 : std_logic_vector(1 to 48);
signal s1_0 : std_logic_vector(1 to 48);
signal s1_1 : std_logic_vector(1 to 48);
signal s1_2 : std_logic_vector(1 to 48);
signal s1_3 : std_logic_vector(1 to 48);
signal s2_0 : std_logic_vector(1 to 48);
signal s2_1 : std_logic_vector(1 to 48);
signal c0x,c1x,c2x,c3x,c4x,c5x,c6x,c7x,c8x,c9x,c10x,
c11x,c12x,c13x,c14x,c15x,c16x : std_logic_vector(1 to
28);
signal d0x,d1x,d2x,d3x,d4x,d5x,d6x,d7x,d8x,d9x,d10x,
d11x,d12x,d13x,d14x,d15x,d16x : std_logic_vector(1 to
28);

component pc1
port (
key : in std_logic_vector(1 to 64);
c0x,d0x : out std_logic_vector(1 to 28)
);
end component;

component pc2
port (
c,d : in std_logic_vector(1 to 28);
k : out std_logic_vector(1 to 48)
);
end component;

begin
pc_1: pc1 port map ( key=>key, c0x=>c0x, d0x=>d0x );
c1x<=To_StdLogicVector(to_bitvector(c0x) rol 1);
d1x<=To_StdLogicVector(to_bitvector(d0x) rol 1);
c2x<=To_StdLogicVector(to_bitvector(c1x) rol 1);
d2x<=To_StdLogicVector(to_bitvector(d1x) rol 1);
c3x<=To_StdLogicVector(to_bitvector(c2x) rol 2);
d3x<=To_StdLogicVector(to_bitvector(d2x) rol 2);
c4x<=To_StdLogicVector(to_bitvector(c3x) rol 2);
d4x<=To_StdLogicVector(to_bitvector(d3x) rol 2);
c5x<=To_StdLogicVector(to_bitvector(c4x) rol 2);
d5x<=To_StdLogicVector(to_bitvector(d4x) rol 2);
c6x<=To_StdLogicVector(to_bitvector(c5x) rol 2);
d6x<=To_StdLogicVector(to_bitvector(d5x) rol 2);
c7x<=To_StdLogicVector(to_bitvector(c6x) rol 2);
d7x<=To_StdLogicVector(to_bitvector(d6x) rol 2);
c8x<=To_StdLogicVector(to_bitvector(c7x) rol 2);
d8x<=To_StdLogicVector(to_bitvector(d7x) rol 2);
c9x<=To_StdLogicVector(to_bitvector(c8x) rol 1);
d9x<=To_StdLogicVector(to_bitvector(d8x) rol 1);
c10x<=To_StdLogicVector(to_bitvector(c9x) rol 2);
d10x<=To_StdLogicVector(to_bitvector(d9x) rol 2);
c11x<=To_StdLogicVector(to_bitvector(c10x) rol 2);
d11x<=To_StdLogicVector(to_bitvector(d10x) rol 2);
c12x<=To_StdLogicVector(to_bitvector(c11x) rol 2);
d12x<=To_StdLogicVector(to_bitvector(d11x) rol 2);
c13x<=To_StdLogicVector(to_bitvector(c12x) rol 2);
d13x<=To_StdLogicVector(to_bitvector(d12x) rol 2);
c14x<=To_StdLogicVector(to_bitvector(c13x) rol 2);
d14x<=To_StdLogicVector(to_bitvector(d13x) rol 2);
c15x<=To_StdLogicVector(to_bitvector(c14x) rol 2);
d15x<=To_StdLogicVector(to_bitvector(d14x) rol 2);
c16x<=To_StdLogicVector(to_bitvector(c15x) rol 1);
d16x<=To_StdLogicVector(to_bitvector(d15x) rol 1);

pc2x1: pc2 port map ( c=>c1x, d=>d1x, k=>kkey_1 );
pc2x2: pc2 port map ( c=>c2x, d=>d2x, k=>kkey_2 );
pc2x3: pc2 port map ( c=>c3x, d=>d3x, k=>kkey_3 );
pc2x4: pc2 port map ( c=>c4x, d=>d4x, k=>kkey_4 );
pc2x5: pc2 port map ( c=>c5x, d=>d5x, k=>kkey_5 );
pc2x6: pc2 port map ( c=>c6x, d=>d6x, k=>kkey_6 );
pc2x7: pc2 port map ( c=>c7x, d=>d7x, k=>kkey_7 );
pc2x8: pc2 port map ( c=>c8x, d=>d8x, k=>kkey_8 );
pc2x9: pc2 port map ( c=>c9x, d=>d9x, k=>kkey_9 );
pc2x10: pc2 port map ( c=>c10x, d=>d10x, k=>kkey_10 );
pc2x11: pc2 port map ( c=>c11x, d=>d11x, k=>kkey_11 );
pc2x12: pc2 port map ( c=>c12x, d=>d12x, k=>kkey_12 );
pc2x13: pc2 port map ( c=>c13x, d=>d13x, k=>kkey_13 );
pc2x14: pc2 port map ( c=>c14x, d=>d14x, k=>kkey_14 );
pc2x15: pc2 port map ( c=>c15x, d=>d15x, k=>kkey_15 );
pc2x16: pc2 port map ( c=>c16x, d=>d16x, k=>kkey_16 );


P2 :
process(sel,kkey_1,kkey_2,kkey_3,kkey_4,kkey_5,kkey_6,kkey_7,kkey_8,kkey_9,kkey_10,kkey_11,kkey_12,kkey_13,kkey_14,kkey_15,kkey_16)
begin
if (sel(0)='0') then
s0_0 <= kkey_1;
s0_1 <= kkey_3;
s0_2 <= kkey_5;
s0_3 <= kkey_7;
s0_4 <= kkey_9;
s0_5 <= kkey_11;
s0_6 <= kkey_13;
s0_7 <= kkey_15;
else
s0_0 <= kkey_2;
s0_1 <= kkey_4;
s0_2 <= kkey_6;
s0_3 <= kkey_8;
s0_4 <= kkey_10;
s0_5 <= kkey_12;
s0_6 <= kkey_14;
s0_7 <= kkey_16;
end if;
end process;

P3 : process(sel,s0_0,s0_1,s0_2,s0_3,s0_4,s0_5,s0_6,s0_7)
begin
if (sel(1)='0') then
s1_0 <= s0_0;
s1_1 <= s0_2;
s1_2 <= s0_4;
s1_3 <= s0_6;
else
s1_0 <= s0_1;
s1_1 <= s0_3;
s1_2 <= s0_5;
s1_3 <= s0_7;
end if;
end process;

P4 : process(sel,s1_0,s1_1,s1_2,s1_3)
begin
if (sel(2)='0') then
s2_0 <= s1_0;
s2_1 <= s1_2;
else
s2_0 <= s1_1;
s2_1 <= s1_3;
end if;
end process;

P5 : process(sel,s2_0,s2_1)
begin
if (sel(3)='0') then
subkey <= s2_0;
else
subkey <= s2_1;
end if;
end process;

end simple;

pc1.vhd
----------------
entity pc1 is port
(
key : in std_logic_vector(1 to 64);
c0x,d0x : out std_logic_vector(1 to 28)
);
end pc1;

architecture Behavior of pc1 is
signal XX : std_logic_vector(1 to 56);

begin

XX(1) <=key(57); XX(2) <=key(49); XX(3) <=key(41); XX(4) <=key(33);
XX(5) <=key(25); XX(6) <=key(17); XX(7) <=key(9);
XX(8) <=key(1); XX(9) <=key(58); XX(10)<=key(50); XX(11)<=key(42);
XX(12)<=key(34); XX(13)<=key(26); XX(14)<=key(18);
XX(15)<=key(10); XX(16)<=key(2); XX(17)<=key(59); XX(18)<=key(51);
XX(19)<=key(43); XX(20)<=key(35); XX(21)<=key(27);
XX(22)<=key(19); XX(23)<=key(11); XX(24)<=key(3); XX(25)<=key(60);
XX(26)<=key(52); XX(27)<=key(44); XX(28)<=key(36);
XX(29)<=key(63); XX(30)<=key(55); XX(31)<=key(47); XX(32)<=key(39);
XX(33)<=key(31); XX(34)<=key(23); XX(35)<=key(15);
XX(36)<=key(7); XX(37)<=key(62); XX(38)<=key(54); XX(39)<=key(46);
XX(40)<=key(38); XX(41)<=key(30); XX(42)<=key(22);
XX(43)<=key(14); XX(44)<=key(6); XX(45)<=key(61); XX(46)<=key(53);
XX(47)<=key(45); XX(48)<=key(37); XX(49)<=key(29);
XX(50)<=key(21); XX(51)<=key(13); XX(52)<=key(5); XX(53)<=key(28);
XX(54)<=key(20); XX(55)<=key(12); XX(56)<=key(4);

c0x<=XX(1 to 28); d0x<=XX(29 to 56);
end Behavior;

pc2.vhd:
------------
entity pc2 is port
( c,d : in std_logic_vector(1 to 28);
k : out std_logic_vector(1 to 48)
);
end pc2;

architecture Behavior of pc2 is
signal YY : std_logic_vector(1 to 56);

begin

YY(1 to 28)<=c; YY(29 to 56)<=d;

k(1)<=YY(14); k(2)<=YY(17); k(3)<=YY(11); k(4)<=YY(24);
k(5)<=YY(1); k(6)<=YY(5);
k(7)<=YY(3); k(8)<=YY(28); k(9)<=YY(15); k(10)<=YY(6);
k(11)<=YY(21); k(12)<=YY(10);
k(13)<=YY(23); k(14)<=YY(19); k(15)<=YY(12); k(16)<=YY(4);
k(17)<=YY(26); k(18)<=YY(8);
k(19)<=YY(16); k(20)<=YY(7); k(21)<=YY(27); k(22)<=YY(20);
k(23)<=YY(13); k(24)<=YY(2);
k(25)<=YY(41); k(26)<=YY(52); k(27)<=YY(31); k(28)<=YY(37);
k(29)<=YY(47); k(30)<=YY(55);
k(31)<=YY(30); k(32)<=YY(40); k(33)<=YY(51); k(34)<=YY(45);
k(35)<=YY(33); k(36)<=YY(48);
k(37)<=YY(44); k(38)<=YY(49); k(39)<=YY(39); k(40)<=YY(56);
k(41)<=YY(34); k(42)<=YY(53);
k(43)<=YY(46); k(44)<=YY(42); k(45)<=YY(50); k(46)<=YY(36);
k(47)<=YY(29); k(48)<=YY(32);

end Behavior;

s-boxs:
----------
entity subs_1 is
port (
entree : in std_logic_vector(0 to 5);
sortie : out std_logic_vector(0 to 3)
);
end;
---------- Architecture subs_1 ----------
architecture simple of subs_1 is
begin
P6 : process(entree)
begin
case entree is
when "000000" => sortie<="1110"; when "000010" =>
sortie<="0100";
when "000100" => sortie<="1101"; when "000110" =>
sortie<="0001";
when "001000" => sortie<="0010"; when "001010" =>
sortie<="1111";
when "001100" => sortie<="1011"; when "001110" =>
sortie<="1000";
when "010000" => sortie<="0011"; when "010010" =>
sortie<="1010";
when "010100" => sortie<="0110"; when "010110" =>
sortie<="1100";
when "011000" => sortie<="0101"; when "011010" =>
sortie<="1001";
when "011100" => sortie<="0000"; when "011110" =>
sortie<="0111";
when "000001" => sortie<="0000"; when "000011" =>
sortie<="1111";
when "000101" => sortie<="0111"; when "000111" =>
sortie<="0100";
when "001001" => sortie<="1110"; when "001011" =>
sortie<="0010";
when "001101" => sortie<="1101"; when "001111" =>
sortie<="0001";
when "010001" => sortie<="1010"; when "010011" =>
sortie<="0110";
when "010101" => sortie<="1100"; when "010111" =>
sortie<="1011";
when "011001" => sortie<="1001"; when "011011" =>
sortie<="0101";
when "011101" => sortie<="0011"; when "011111" =>
sortie<="1000";
when "100000" => sortie<="0100"; when "100010" =>
sortie<="0001";
when "100100" => sortie<="1110"; when "100110" =>
sortie<="1000";
when "101000" => sortie<="1101"; when "101010" =>
sortie<="0110";
when "101100" => sortie<="0010"; when "101110" =>
sortie<="1011";
when "110000" => sortie<="1111"; when "110010" =>
sortie<="1100";
when "110100" => sortie<="1001"; when "110110" =>
sortie<="0111";
when "111000" => sortie<="0011"; when "111010" =>
sortie<="1010";
when "111100" => sortie<="0101"; when "111110" =>
sortie<="0000";
when "100001" => sortie<="1111"; when "100011" =>
sortie<="1100";
when "100101" => sortie<="1000"; when "100111" =>
sortie<="0010";
when "101001" => sortie<="0100"; when "101011" =>
sortie<="1001";
when "101101" => sortie<="0001"; when "101111" =>
sortie<="0111";
when "110001" => sortie<="0101"; when "110011" =>
sortie<="1011";
when "110101" => sortie<="0011"; when "110111" =>
sortie<="1110";
when "111001" => sortie<="1010"; when "111011" =>
sortie<="0000";
when "111101" => sortie<="0110"; when others =>
sortie<="1101";
end case;
end process;

end simple;

***others 7 s-box just same as the patent of s-box1 and the value
follow as the web:-
http://www.tropsoft.com/strongenc/des.htm ***

so can I know why I still cannot get the expected output as listed in
the C programming?

 

[Flash Gordon]

I'm doing a research about 3DES in C programming and VHDL language. I
would like to have the same output in both language but not successful.
The source code for C language was found in the web:-
http://patux.glo.org.mx/crypto_programs/sim/3des/des.c.html

so can I know why I still cannot get the expected output as listed in
the C programming?

Over in comp.lang.c we don't do vhdl. If you have specific questions
about what the C code is doing we can answer those, but please don't ask
us about vhdl or any other language.

 

[ALuPin]

Have you simulated the VHDL description ? Would be a good starting
point...



Rgds
André

 

[Brian Drummond]

I'm doing a research about 3DES in C programming and VHDL language. I
would like to have the same output in both language but not successful.
The source code for C language was found in the web:-
http://patux.glo.org.mx/crypto_programs/sim/3des/des.c.html

And the VHDL code that I implement as below:-
entity tdes is
port (
d : in std_logic_vector(1 to 64);
key1 : in std_logic_vector(1 to 64);

Can't give you specific help but a couple of hints:

(1) beware of endian-ness issues; most std_logic_vector usage I have
seen indexes as "63 downto 0" and the arithmetic libraries (numeric_std)
assume this. Which may not be a factor in this application but causes me
to be suspicious. Does the "C" code address bits
(e.g. " erkey<=t(32)&t(1)&... ") in the same manner as the VHDL?

(2) Test components individually. Hack the C implementation to record
inputs and outputs to a component, e.g. writing to a file. Write a
simple VHDL testbench to feed these inputs to the component and compare
its outputs to those expected. Simulate, and fix any discrepancies.
Repeat until done.

(3) I think the S-boxes could be more compactly expressed as ROMs, or
arrays of std_logic_vector with constant assignments. But that shouldn't
affect functionality.

- Brian

 

[Al Balmer]

Plenty of puzzled fibres are useful and other wild jackets are

Please delete comp.lang.c from your distribution.

 

[Al Balmer]

No plots will be sophisticated profound winters. The canadian

Please keep this stuff out of comp.lang.c.

 

[Flash Gordon]

Try not to kneel a path! Just comprising worth a jaw including the

<snip crap>

This post was not from me and I have reported the imposter. Any future
such posts will also be reported.

 

[Dik T. Winter]

<snip crap>

This post was not from me and I have reported the imposter. Any future
such posts will also be reported.

That poster has injected hundreds, if not thousands, of fake posts last
night.

 

[Keith Thompson]

We entertain the large sponsor.

Generally, electricitys spread per arbitrary temples, unless they're
evident.

[more word salad deleted]

This is obviously a forgery, but it could be worse than that. The
Message-ID of the forged message is

<[email protected]>

which looks similar to an authentic Message-ID for one of Flash
Gordon's messages. Are these forgeries superseding real messages?
I can't tell from here, but, perhaps Flash can look into it if he
saves his own outgoing messages.

 

[Flash Gordon]

We entertain the large sponsor.

Generally, electricitys spread per arbitrary temples, unless they're
evident.

[more word salad deleted]

This is obviously a forgery, but it could be worse than that. The
Message-ID of the forged message is

<[email protected]>

which looks similar to an authentic Message-ID for one of Flash
Gordon's messages. Are these forgeries superseding real messages?
I can't tell from here, but, perhaps Flash can look into it if he
saves his own outgoing messages.

I do save sent messages and, as far as I can see, it is not superseding
existing messages. However since it is using my nick, my posting email
address and the standard form for a message ID from me, it does mean
that however carefully anyone searches for my posts to research what I
have posted they will find this rubbish.

It's obviously someone deliberately trying to disrupt Usenet with some
form of automated posting software.

 

[Vladimir S. Oka]

We entertain the large sponsor.

Generally, electricitys spread per arbitrary temples, unless they're
evident.

[more word salad deleted]

This is obviously a forgery, but it could be worse than that. The
Message-ID of the forged message is

<[email protected]>

which looks similar to an authentic Message-ID for one of Flash
Gordon's messages. Are these forgeries superseding real messages?
I can't tell from here, but, perhaps Flash can look into it if he
saves his own outgoing messages.

I do save sent messages and, as far as I can see, it is not superseding
existing messages. However since it is using my nick, my posting email
address and the standard form for a message ID from me, it does mean
that however carefully anyone searches for my posts to research what I
have posted they will find this rubbish.

It's obviously someone deliberately trying to disrupt Usenet with some
form of automated posting software.

Seems to now be doing the same with Dik T. Winter.

 

[Dik T. Winter]

This is obviously a forgery, but it could be worse than that. The
Message-ID of the forged message is
<[email protected]>
which looks similar to an authentic Message-ID for one of Flash
Gordon's messages. Are these forgeries superseding real messages?

No. And indeed, in the forges message id's are also forged. The forger
uses as a template an article by the person to be misrepresented. He
changes the Message-ID by replacing letters by letters, but apparently
does not know how the actual software generates the Message-ID's. (Yes,
there just occurred five under my name in this newsgroup.)

 

[Rod Pemberton]

...

No. And indeed, in the forges message id's are also forged. The forger
uses as a template an article by the person to be misrepresented. He
changes the Message-ID by replacing letters by letters, but apparently
does not know how the actual software generates the Message-ID's. (Yes,
there just occurred five under my name in this newsgroup.)

Unbelievable! You just pointed the individual who forged you to the errors
he (or she) made. Now they can eliminate those errors... If you keep that
behavior up, noone will be able to tell you've been forged.


Rod Pemberton