incompatible ouput files

[koyel.aphy]

I have a strange problem that in the following code, I see correct
result in the simulation wave window of modelsim but the ouput file
written shows a wrong output value, which is the first output and rest
are correct. So the pproblem is while wrting the outputs to the file
but I am not able to understand the problem. Could anyone please help
in pointing that out? This is no test bench but this code does
testing on the hardware and I have just added the writefile operation
to that in order to get the outputs in a file.Also the strange thing
is the ouputs obtained in binary form in another file shows correct
result but not in the one where it is converted to integer but again
that's only the first output value out of 1024. file outacm1 has the
first value of the first row incorrect whereas outacmr1, which is a
binary output gives correct value for the same.Following is the code
where I get the output in a file and the inputs are not read from any
file but generated by an array containing them. So I do not need any
input other than clock and reset though I do not think the code can be
of much use in understanding the problem. Under what circumstances
such problem can arise?

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;
use work.myram1024.all;
entity xacmtop is
port(clk,reset : in std_logic;
blank : in std_logic:='0';
oacr1,oacr2,oaci1,oaci2 : out std_logic_vector(DATA_WIDTH -1
downto 0):=(others=>'0');
--read_add: in std_logic_vector(ADDRESS_WIDTH - 1 downto 0);
indexr1,indexr2,indexi1,indexi2 : out
std_logic_vector(ADDRESS_WIDTH -1 downto 0));
end xacmtop;
architecture archi of xacmtop is
component xacm11024
port(xr,xi,yr,yi : in std_logic_vector(21 downto 0):=(others=>'0');
oacr1,oacr2,oaci1,oaci2 : out std_logic_vector(DATA_WIDTH -1
downto 0):=(others=>'0');
clk,reset,reade : in std_logic;
blank : in std_logic:='0';
--read_add: in std_logic_vector(ADDRESS_WIDTH - 1 downto 0);
indexi: in std_logic_vector(ADDRESS_WIDTH -1 downto 0);
indexr1,indexr2,indexi1,indexi2 : out
std_logic_vector(ADDRESS_WIDTH -1 downto 0));
end component;
--component acmdat
--port(clk: in std_logic;
-- reset: in std_logic;
-- reset1: out std_logic;
-- indexin : out std_logic_vector(ADDRESS_WIDTH - 1 downto 0);
-- xr,yr,xi,yi : out std_logic_vector(21 downto 0):=(others=>'0'));
--end component;
component acmdat1
port(
clock,reset: in std_logic;
reset1,reade : out std_logic;
xr,xi,yr,yi : out std_logic_vector(21 downto 0):=(others=>'0');
index: out std_logic_vector(ADDRESS_WIDTH - 1 downto
0):=(others=>'0'));
end component;
signal reset1,reade : std_logic;
signal indxin : std_logic_vector(ADDRESS_WIDTH - 1 downto 0);
signal sxr,syr,sxi,syi : std_logic_vector(21 downto 0):=(others=>'0');
SIGNAL valid_data_write : BOOLEAN := FALSE;
signal acmr1,acmr2,acmi1,acmi2 : std_logic_vector(DATA_WIDTH - 1
downto 0):=(others=>'0');
begin
u1:acmdat1 port map(clk,reset,reset1,reade,sxr,sxi,syr,syi,indxin);
--u1 : acmdat port map(clk,reset,reset1,indxin,sxr,syr,sxi,syi);
u2 : xacm11024 port
map(sxr,sxi,syr,syi,acmr1,acmr2,acmi1,acmi2,clk,reset1,reade,blank,indxin,indexr1,indexr2,indexi1,indexi2);
oacr1<=acmr1;
oacr2<=acmr2;
oaci1<=acmi1;
oaci2<=acmi2;
process(clk,reset)
begin
if(clk'event and clk='1') then
if reade = '1' then
valid_data_write <= TRUE;
elsif reade = '0' then
valid_data_write <= FALSE;
end if;
end if;
end process;
Writefile : PROCESS
file outacm1:TEXT open WRITE_MODE is "outacm1.txt";
VARIABLE outline : LINE;
file outacmr1:TEXT open WRITE_MODE is "outacmr1.txt";
VARIABLE outline1 : LINE;
file outacmr2:TEXT open WRITE_MODE is "outacmr2.txt";
VARIABLE outline2 : LINE;
file outacmi1:TEXT open WRITE_MODE is "outacmi1.txt";
VARIABLE outline3 : LINE;
file outacmi2:TEXT open WRITE_MODE is "outacmi2.txt";
VARIABLE outline4 : LINE;
BEGIN

WAIT UNTIL clk = '1' AND clk'EVENT;

IF (valid_data_write = TRUE) THEN
WRITE(outline, STRING'(""));
WRITE(outline, to_integer(signed(acmr1)));
WRITE(outline, STRING'(", "));
WRITE(outline, to_integer(signed(acmr2)));
WRITE(outline, STRING'(", "));
WRITE(outline, to_integer(signed(acmi1)));
WRITE(outline, STRING'(", "));
WRITE(outline, to_integer(signed(acmi2)));
--WRITE(outline, STRING'(" index = "));
--WRITE(outline, index);
WRITELINE(outacm1, outline);
END IF;
IF (valid_data_write = TRUE) THEN
WRITE(outline1, STRING'("('"));
WRITE(outline1, acmr1);
WRITE(outline1, STRING'("'),"));
WRITELINE(outacmr1,outline1);
END IF;
IF (valid_data_write = TRUE) THEN
WRITE(outline2, STRING'("('"));
WRITE(outline2, acmr2);
WRITE(outline2, STRING'("'),"));
WRITELINE(outacmr2, outline2);
END IF;
IF (valid_data_write = TRUE) THEN
WRITE(outline3, STRING'("('"));
WRITE(outline3, acmi1);
WRITE(outline3, STRING'("'),"));
WRITELINE(outacmi1,outline3);
END IF;
IF (valid_data_write = TRUE) THEN
WRITE(outline4, STRING'("('"));
WRITE(outline4, acmi2);
WRITE(outline4, STRING'("'),"));
WRITELINE(outacmi2, outline4);
END IF;
END PROCESS Writefile ;
end archi;

Best Regards

 

[Mike Treseler]

I have a strange problem that in the following code, I see correct
result in the simulation wave window of modelsim but the ouput file
written shows a wrong output value, which is the first output and rest
are correct. So the pproblem is while wrting the outputs to the file
but I am not able to understand the problem. Could anyone please help
in pointing that out? This is no test bench but this code does
testing on the hardware and I have just added the writefile operation
to that in order to get the outputs in a file.

Doing 'testing on the hardware' is what a testbench does.
Consider using vhdl assertions instead of textio.

-- Mike Treseler

 

[koyel.aphy]

Doing 'testing on the hardware' is what a testbench does.
Consider using vhdl assertions instead of textio.

Okay thanks for this information that is new to me unless I try to
correlate the word 'test bench' with testing as the ones I have
encountered in some textbooks are only for simulation purpose.

I will try to use the vhdl assertions, which also I have to look at as
I have never used that before.

Best Regards

 

[Mike Treseler]

Okay thanks for this information that is new to me unless I try to
correlate the word 'test bench' with testing as the ones I have
encountered in some textbooks are only for simulation purpose.

It seems to me, that if you are using modelsim,
you are doing simulation.

-- Mike Treseler