titi said:
In the following example, what would do the xxx assignment?
"Do" in terms of behavior? -> Use a simulator.
"Do" in terms of synthesis? -> Use a synthesis tool and have a look.
What would be the effect of removing the xxx and doing direct assignment?
process(Reset,Pulse,e1,Val)
begin
if Reset ='1' then
result <= "0000";
elsif Pulse ='1' and Val = 25 then
xxx <= e1(3 downto 0);
result <= xxx;
end if;
end process;
xxx will become a latch (this means a memory element) if you read xxx
somewhere else. If you don't read it somewhere else then the synthesis
tool will remove xxx because it is useless.
As Pieter states the sensitivity list is incomplete. If you add xxx to
it, you will observe during simulation that e1 will be feed through to
result via xxx. Note that synthesis and simulation will result in
different behavior with an incomplete sensitivity list!
Let me add: result is a latch and you will run into the muxed-latch
problem. This means, a mux choses the value to load into a latch, but
both the mux-selector as well as the latch-enable are driven by the same
signals. If the latch-enable becomes inactive, the mux may change its
output too and this may be faster than closing the latch. To get rid of
this, seperate the mux-selector and the latch-enable! How to do it is
your task. I can only give you the hint, that the mux chooses between
"0000" and e1(3 downto 0) and the latch is loaded with the output of the
mux if reset='1' or if (pulse='1' and val=25). You have to find some
_different_ signal that serves as the mux-selector! A signal, that is
stable if reset becomes inactive AND pulse becomes inactive AND val gets
a different value.
Latches are wonderful for low-power small-area designs, but as you see
they are difficult to handle.
Ralf