Inference Information in ModelSim

[Andrew Greensted]

Hi All,

One of the more useful parts of the Xilinx ISE tools is that the
Synthesis Report gives details of what macros (counters, shift
registers, FSMs) have been inferred when a design is synthesised.

My question is, is it possible to get modelSim to provide this information?

- This information is useful as a quick sanity check that your design is
actually describing what you think it is.
- It also shows up (this being very useful) if you've missed a signal
assignment in the combinatorial part of a two process FSM. Helping
remove any registers that have been inferred.

Many Thanks
Andy

--
Dr. Andrew Greensted Department of Electronics
Bio-Inspired Engineering University of York, YO10 5DD, UK

Tel: +44(0)1904 432379 Mailto: (e-mail address removed)
Fax: +44(0)1904 433224 Web: www.bioinspired.com/users/ajg112

 

[Brian Drummond]

Hi All,

One of the more useful parts of the Xilinx ISE tools is that the
Synthesis Report gives details of what macros (counters, shift
registers, FSMs) have been inferred when a design is synthesised.

My question is, is it possible to get modelSim to provide this information?

Hardly; ModelSim is a simulator.

The ISE report describes what the synthesis tool has inferred; clearly
that won't work without a synthesis tool. One of its functions is as a
sanity check on the synthesis tool itself, as well as your code; it is
entirely possible for a synthesis tool to generate strange results (e.g.
a very large number of flipflops instead of a Block RAM). Another is to
tune results so that some multiplication operators use multiplier blocks
while others use gates.

But in any case the results are so intimately tied in to the synthesis
process that any results without synthesis would be meaningless.

- Brian

 

[Mike Treseler]

One of the more useful parts of the Xilinx ISE tools is that the
Synthesis Report gives details of what macros (counters, shift
registers, FSMs) have been inferred when a design is synthesised.
My question is, is it possible to get modelSim to provide this information?

No, but if you base your design on the
vhdl synchronous process, modelsim and
some testbench coding will tell you if
your design will work as you expect on the bench.

- This information is useful as a quick sanity check that your design is
actually describing what you think it is.

This is a sanity check on synthesis
design rules, not on the design function.
For a complex design I need to trust
my design rules and tools well enough
that a functional sim is an
adequate design verification.

If this is ever not the case,
I update my rules.

-- Mike Treseler

 

[Muralidharan]

The Xilinx ISE is able give the information because it knows the target
device (you select it when start the project) and the synthesis will
try to infer the available components. But in case of ModelSim it is
only a simulator and will tell you whether your logic works or not.
Of course as you have said the info is useful to see how your logic
pans out in a hardware but once you are familiar with coding and coding
guidelines it would not be of much help.

 

[Andy]

If you don't use two process FSMs, then you won't have problems with
missed signal assignments causing latches.

Andy

 

[Andrew Greensted]

Thanks all for your answers
Andy

--
Dr. Andrew Greensted Department of Electronics
Bio-Inspired Engineering University of York, YO10 5DD, UK

Tel: +44(0)1904 432379 Mailto: (e-mail address removed)
Fax: +44(0)1904 433224 Web: www.bioinspired.com/users/ajg112