Initializing array of vectors VHDL

[mbrook10]

How do you initialize an array of vectors. I tried doing it and for some reason nothing in my array is not being set. Below is part of my code.

architecture behv of CPU_Memory is
type memory is array(0 to 1023) of std_logic_vector(7 downto 0);
signal memory_address : memory;
begin
memory_address(0) <= "00000000";
memory_address(1) <= "00000000";
memory_address(1) <= "00000000";
memory_address(3) <= "00000000";
process(datain, address, rd, wr, clk, en)
variable index: integer;
begin
if(clk = '1' and en = '1') then
index := conv_integer(address);
if(rd = '1') then
dataout(31 downto 24) <= memory_address(index);
dataout(23 downto 16) <= memory_address(index+1);
dataout(15 downto 8 ) <= memory_address(index+2);
dataout(7 downto 0) <= memory_address(index+3);
.....
....
....
...
When I run a testbench and see what is in memory_address (0), 1, 2, and 3 it returns all U's.

 

[ttg1003]

just to initialize an array of vectors for example with zeros you would need this line of code (you may as well add a Reset and initialize all internal signals and outputs upon reset):

memory_address <= (others=> (others=>'0'));

Also it is good idea to work on a clock event other than only clock value - this might be the reason of getting the 'u''s