inout std_logic_vector to array of std_logic_vector of generic length conversion...

[Thomas Rouam]

Hi all,

I have an issue converting inouts. Any help or even idea is welcome,
as I'm getting desperate.

Here is the description of my problem.

Say I have this component :

component my_component is
generic ( my_generic : integer);
port (component_data : inout std_logic vector ((8*my_generic) -1
downto 0);
others ports : ....
etc : .....);

Say I have this top level

entity my_top_level is
generic ( my_generic : integer := my_constant);
port (top_level_data : my_2d_type(my_generic downto 1);
other ports : ......
etc : .......)
where my_constant and my_2d_type are defined in a used package,
my_2d_type being : array (natural range <>) of std_logic_vector(7
downto 0);

I want to "connect" and of course not "assign" component_dat with
top_level_data.

To solve this problem I have thougth of concatenations, aliases,
functions, procedures and even recursive structures, but each time
something is wrong (2d-aliases, locally static name, inout and
expressions, and so on...

Thanks a lot for the help

Thomas Rouam

 

[Tricky]

Hi all,

I have an issue converting inouts. Any help or even idea is welcome,
as I'm getting desperate.

Here is the description of my problem.

Say I have this component :

component my_component is
generic ( my_generic : integer);
port (component_data : inout std_logic vector ((8*my_generic) -1
downto 0);
others ports : ....
etc : .....);

Say I have this top level

entity my_top_level is
generic ( my_generic : integer := my_constant);
port (top_level_data : my_2d_type(my_generic downto 1);
other ports : ......
etc : .......)
where my_constant and my_2d_type are defined in a used package,
my_2d_type being : array (natural range <>) of std_logic_vector(7
downto 0);

I want to "connect" and of course not "assign" component_dat with
top_level_data.

To solve this problem I have thougth of concatenations, aliases,
functions, procedures and even recursive structures, but each time
something is wrong (2d-aliases, locally static name, inout and
expressions, and so on...

Thanks a lot for the help

Thomas Rouam

If the inout connects within the design internally, change it to
separate IN and an OUT ports. INOUT ports internally will probably be
synthesized to separate IN and OUT signals anyway, as they require the
use of tri-states which are no longer used inside modern FPGAs (Except
on Pins).

If its connecting to an external device, keep it as the top level
vector size until you are at the processing end of the wire, then
convert it into my_2d_type at the bottom of the hierarchy.

Otherwise, try this:


signal my_wire : std_logic_vector(;
signal temp_data : std_logic_vector ((8*my_generic) -1 downto 0);
begin
...
...
wire_gen : for i in 1 to my_generic generate
my_wire(i) <= temp_data((i*8) -1 downto
(i-1)*8);
temp_data((i*8) -1 downto (i-1)*8) <= my_wire(i);
end generate wire_gen;

comp_inst : my_component
.....
port map (
component_data => temp_data,
...
...
);

top_level_data <= my_wire;
my_wire <= top_level_data;


This is allowable because the std_logic type is resolved and allows
multiple drivers, but a driving value of 'Z' is required at 1 end of
the connection at all times, otherwise you'll have 'X' turn up in
simulation, or all sorts of crap on hardware. Remember to put tri-
states on both ends of the buses.

Id still recommend using separate IN and OUT ports though.

 

[Tricky]

*signal my_wire : std_logic_vector(;*

errr, that should be

signal my_wire : my_2d_type(my_generic downto 1);

 

[KJ]

Hi all,

I have an issue converting inouts. Any help or even idea is welcome,
as I'm getting desperate.

Here is the description of my problem.

Say I have this component :

component my_component is
generic ( my_generic : integer);
port (component_data : inout std_logic vector ((8*my_generic) -1
downto 0);
others ports : ....
etc : .....);

Say I have this top level

entity my_top_level is
generic ( my_generic : integer := my_constant);
port (top_level_data : my_2d_type(my_generic downto 1);
other ports : ......
etc : .......)
where my_constant and my_2d_type are defined in a used package,
my_2d_type being : array (natural range <>) of std_logic_vector(7
downto 0);

I want to "connect" and of course not "assign" component_dat with
top_level_data.

To solve this problem I have thougth of concatenations, aliases,
functions, procedures and even recursive structures, but each time
something is wrong (2d-aliases, locally static name, inout and
expressions, and so on...

Thanks a lot for the help

Thomas Rouam

The following should connect up top_level_data(1) to 'my_component'

An_Inst_Of_My_Component : my_component
generic map(my_generic => my_generic)
port map(component_data => top_level_data(1));

If you want to have an instance of 'my_component' for each element of
top_level_data then...

Gen_A_Bunch : for i in top_level_data'range generate
An_Inst_Of_My_Component : my_component
generic map(my_generic => my_generic)
port map(component_data => top_level_data(i));
end generate Gen_A_Bunch;

KJ

 

[Thomas Rouam]

The following should connect up top_level_data(1) to 'my_component'

An_Inst_Of_My_Component : my_component
generic map(my_generic => my_generic)
port map(component_data => top_level_data(1));

If you want to have an instance of 'my_component' for each element of
top_level_data then...

Gen_A_Bunch : for i in top_level_data'range generate
An_Inst_Of_My_Component : my_component
generic map(my_generic => my_generic)
port map(component_data => top_level_data(i));
end generate Gen_A_Bunch;

KJ- Hide quoted text -

- Show quoted text -

This approach is OK if component data is the only port, here I've got
loads of other port that have to be synthesized just once. That's why
I need only ONE instance of my_component.

 

[Thomas Rouam]

If the inout connects within the design internally, change it to
separate IN and an OUT ports. INOUT ports internally will probably be
synthesized to separate IN and OUT signals anyway, as they require the
use of tri-states which are no longer used inside modern FPGAs (Except
on Pins).

If its connecting to an external device, keep it as the top level
vector size until you are at the processing end of the wire, then
convert it into my_2d_type at the bottom of the hierarchy.

Otherwise, try this:

signal my_wire : std_logic_vector(;
signal temp_data : std_logic_vector ((8*my_generic) -1 downto 0);
begin
..
..
wire_gen : for i in 1 to my_generic generate
my_wire(i) <= temp_data((i*8) -1 downto
(i-1)*8);
temp_data((i*8) -1 downto (i-1)*8) <= my_wire(i);
end generate wire_gen;

comp_inst : my_component
....
port map (
component_data => temp_data,
..
..
);

top_level_data <= my_wire;
my_wire <= top_level_data;

This is allowable because the std_logic type is resolved and allows
multiple drivers, but a driving value of 'Z' is required at 1 end of
the connection at all times, otherwise you'll have 'X' turn up in
simulation, or all sorts of crap on hardware. Remember to put tri-
states on both ends of the buses.

Id still recommend using separate IN and OUT ports though.- Hide quoted text -

- Show quoted text -

Tricky,

I did think of your approach. This does some sort of work yes. I do
say some sort because if you do not flatten the hierarchy when
synthesizing, it doesn't saying multiple drivers for the same signal,
even if I do know that it would work. If I had the choice of
everything, of course, I would have kept my my_2d_type from the top
level down the hierarchy where I would have used it, but unfortunately
this is not the case. I'm just allowed to instantiate my_component.

Thanks for your answer.

 

[KJ]

This approach is OK if component data is the only port, here I've got
loads of other port that have to be synthesized just once. That's why
I need only ONE instance of my_component.- Hide quoted text -

Ports don't get synthesized, instances do. So saying that you have
'loads of other port that have to be synthesized just once' means
absolutely nothing.

From your problem description you simply said you were having trouble

connecting up the ports for your 2d array type so I showed you how to
do it. The fact that your top level entity has a 2d array/vector
structure and your component has an interface for only a 1d vector
implies that you either:
- Need an array of instances (which is what I showed how to generate
and connect)
- Change your component interface to have a 2d array/vector (if you
are only instantiating your component once for whatever your reasons
may be). If the component interface is changed to have a 2d array as
it is in the top level, then connecting the ports is trivial.
- Time multiplex the 1d vector signals of your component into flops
and muxes at the top level to distribute them into the 2d array.

There are no other choices.

KJ