Interface on CPU data bus

[Norbert Hoppe]

Hi group,

i have a problem using a CPLD as an interface between a cpu
and a CAN controller. It is my first CPLD project so maybe
it is a common newbee problem.
The CPLD (see VHDL code at the bottom) should
- get the information from the data bus when
- nCS3 has a falling edge
- at addr 100 to 111
- write the information onto the data bus when
- nCS3 is low
- at addr 000 to 011

Tool: Xilinx ISE Version 6.1.03i
OS: Win2k

The syntesizer report says under HDL Synthesis:

WARNING:Xst:647 - Input <addr<1:0>> is never used.
WARNING:Xst:647 - Input <RS_Ready> is never used.
WARNING:Xst:646 - Signal <data_i<23:18>> is assigned but never used.
WARNING:Xst:646 - Signal <data_i<16>> is assigned but never used.
WARNING:Xst:646 - Signal <data_out> is assigned but never used.
Found 1-bit register for signal <can_stdby>.
Found 24-bit tristate buffer for signal <data>.
Summary:
inferred 1 D-type flip-flop(s).
inferred 24 Tristate(s).
Unit <can_interface> synthesized.


A look at the RTL Schematic shows that the second process was
ignored.

What went wrong?
Thanks in advance.

Norbert



library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity can_interface is
Port (
-- -- -- -- -- -- -- -- pins that are connected to the sja1000
can_stdby: out std_logic := '0';
-- -- -- -- -- -- -- -- pins that are connected to the cpu
data : inout std_logic_vector(23 downto 0);
addr : in std_logic_vector(2 downto 0);
nCS3 : in std_logic;
RS_Ready : in std_logic
);
end can_interface;

architecture Behavioral of can_interface is

signal data_in: std_logic_vector(15 downto 0) := (others => '0');
signal data_i : std_logic_vector(23 downto 0);

-- register for the data to be send to the CPU data bus
signal data_out: std_logic_vector(15 downto 0) := (others => '0');

begin

-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- CPLD read the CPU data bus on addr 100 until 111
P_R_Data: process( nCS3, addr(2), data_i)
begin
if nCS3='0' and nCS3'event and addr(2) = '1' then
data_in <= data_i(15 downto 0);
can_stdby <= data_i(17);
end if;
end process P_R_Data;

data_i <= data;
data_out <= data_in;

-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- CPLD writes the CPU data bus on addr 000 until 011
P_W_Data: process( nCS3, addr, RS_Ready, data_out)
begin
if nCS3='0' then
if addr(2) = '0' then
case addr(1 downto 0) is
when "00" =>
data(15 downto 0) <= data_out;
data(23) <= RS_Ready;
data <= (others => '0');
when others =>
data <= (others => '0');
end case;
else data <= (others => 'Z');
end if;
else data <= (others => 'Z');
end if;
end process P_W_Data;

end Behavioral;