is it possible to have a clockless design synthesizeable?

[niyander]

hi,

can any one please tell me that is it possible to synthesize a
clockless design, 100% working?
few days back i was reading a book on vhdl, there author quoted an
example of floating point adder and in that example clock was not
used.

thanks

 

[backhus]

hi,

can any one please tell me that is it possible to synthesize a
clockless design, 100% working?
few days back i was reading a book on vhdl, there author quoted an
example of floating point adder and in that example clock was not
used.

thanks

Hi,
sure it is possible.
I does not always make sense, but possible it is.

When you are reading abooks on VHDL, keep in mind that there are now
several target technologies that can be used for HDL designs.
e.g. CPLDs, FPGAs and ASICs.
Each has its special strengths and weaknesses.

Large combinatorical blocks like the mentioned example are good for
ASICs, where FFs are expensive and silicon is fast with a fine logic
granulation (down to single gates).
While in FPGAs FFs are cheap and logic granulation is higher (4 or 6
input LUTs). Best performance is acheived here by using pipelined
architectures.

Have a nice synthesis
Eilert

 

[debayan_p]

Hey, just think in very simple terms!

Suppose I design a 4:1 MUX with VHDL/Verilog. Now this design would be clock-less...right?

Of course Synopsys DA or some FPGA tools would allow you to do the synthesis.