Is it possible to write functions in VHDL with implicit parameters?

[G Iveco]

Hello there,

Following code I want to convert std_logic_vector of any bit-width into
signed
numbers. My need is that it should be versatile as I can't code same
function
for every bit-width..

Thank you for your ideas.


function slv_2_signed(
data: in std_logic_vector)
return signed is
variable index : integer;
variable data_signed: signed(data'range-1 downto 0);
begin
for index in data'range loop
data_signed(index) := data(index);
end loop;
return data_signed;
end function slv_2_signed;





In Modelsim, I see the following errors.

# ** Error: ../TB/coms_fir_sim.vhd(121): (vcom-1078) Identifier "signed" is
not directly visible.
# Potentially visible declarations are:
# ieee.numeric_bit.signed (type declaration)
# ieee.std_logic_arith.signed (type declaration)
# ** Error: ../TB/coms_fir_sim.vhd(121): Function cannot return anonymous
subtype.
# ** Error: ../TB/coms_fir_sim.vhd(123): Attribute name with designator
"range" cannot be left operand of infix expression "-".
# ** Error: ../TB/coms_fir_sim.vhd(123): Illegal use of range.
# ** Error: ../TB/coms_fir_sim.vhd(123): Bad expression in left bound of
range expression.
# ** Error: ../TB/coms_fir_sim.vhd(123): (vcom-1078) Identifier "signed" is
not directly visible.
# Potentially visible declarations are:
# ieee.numeric_bit.signed (type declaration)
# ieee.std_logic_arith.signed (type declaration)
# ** Error: ../TB/coms_fir_sim.vhd(137): No feasible entries for subprogram
"to_integer".
# ** Error: ../TB/coms_fir_sim.vhd(174): VHDL Compiler exiting
# C:/Programs/Modeltech_xe_starter/win32xoem/vcom failed.

 

[Ralf Hildebrandt]

Following code I want to convert std_logic_vector of any bit-width into
signed
numbers.

use IEEE.Numeric_std.all;

my_signed<=signed(my_std_ulogic_vector);

Ralf

 

[Jonathan Bromley]

Hello there,

Following code I want to convert std_logic_vector of any bit-width into
signed
numbers. My need is that it should be versatile as I can't code same
function
for every bit-width..

Because SIGNED and STD_LOGIC_VECTOR are both defined as arrays
of std_logic indexed by NATURAL, they are "closely related types"
and you can convert one to the other freely:

signed_var := signed(slv_expression);
slv_var := std_logic_vector(signed_expression);

However, from the errors you show, it seems that you have
tried to USE std_logic_arith and numeric_std packages in
the same design - a very bad idea. Get rid of std_logic_arith.

All VHDL subprograms can have unconstrained parameters,
and functions can have unconstrained return types. So
your (basically correct, but unnecessary) conversion
function would look like this:

function to_signed(v: std_logic_vector) return signed is
variable s: signed(v'range);
begin
for i in v'range loop
s(i) := v(i);
end loop;
return s;
end;

And it would work correctly on any size of std_logic_vector,
returning a signed result of the same size.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
(e-mail address removed)
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[G Iveco]

Because SIGNED and STD_LOGIC_VECTOR are both defined as arrays
of std_logic indexed by NATURAL, they are "closely related types"
and you can convert one to the other freely:

signed_var := signed(slv_expression);
slv_var := std_logic_vector(signed_expression);

However, from the errors you show, it seems that you have
tried to USE std_logic_arith and numeric_std packages in
the same design - a very bad idea. Get rid of std_logic_arith.

Thank you very much, but it didn't seem to work out..
I removed std_logic_arith, Modelsim complains illegal type conversion.
I tried to_integer(signed(to_stdulogicvector(filt))) also, no luck.

write(trace_line, to_integer(signed(filt)));
writeline(log, trace_line);


# ** Error: ../TB/coms_fir_sim.vhd(137): Illegal type conversion from
ieee.std_logic_1164.std_logic_vector to ieee.numeric_bit.signed (array
element type difference).
# ** Error: ../TB/coms_fir_sim.vhd(174): VHDL Compiler exiting
# C:/Programs/Modeltech_xe_starter/win32xoem/vcom failed.

This is my library declarations..


library IEEE;
LIBRARY std_developerskit;
use IEEE.std_logic_1164.all;
use IEEE.numeric_bit.all;
use std.textio.all;
USE std_developerskit.std_iopak.all;

All VHDL subprograms can have unconstrained parameters,
and functions can have unconstrained return types. So
your (basically correct, but unnecessary) conversion
function would look like this:

function to_signed(v: std_logic_vector) return signed is
variable s: signed(v'range);
begin
for i in v'range loop
s(i) := v(i);
end loop;
return s;
end;

And it would work correctly on any size of std_logic_vector,
returning a signed result of the same size.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
(e-mail address removed)
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

Tried the function, it's works! The assignment line needs some modification
as follows:

s(i) := to_bit(v(i));

 

[Ralf Hildebrandt]

G Iveco schrieb:

Thank you very much, but it didn't seem to work out.. ....
use IEEE.numeric_bit.all;

replace this with:

use IEEE.Numeric_std.all;


Btw:: Have a look into Numeric_std. It is not difficult to understand
and gives some nice hints for the solution of silimar problems.

Ralf