It urgent for me!!!

[Kumar]

Hi I am new to VHDL proramming ...
Can anybody tell me how to code for the


4 bit updown counter
(a) behavioural arch
(b) structural arch





Please reply please please!!!!!

 

[Srinivasan Venkataramanan]

Oh great, so how many marks/credits are assigned for this home work? If it
is not homework, and you are trying to learn - the best way to learn is to
code yourself and learn it and NOT by asking some one else. BTW, there is
some thing called google - if you didn't know that before.

Srini
P.S. Sorry for being blunt - read and develop your skills from books,
tutorials and then ask for specific help in these forums. Online forums are
NOT replacement to hardwork, book reading etc.

--
Srinivasan Venkataramanan
Co-Author: SystemVerilog Assertions Handbook, http://www.abv-sva.org
Co-Author: Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition.
http://www.noveldv.com
I own my words and not my employer, unless specifically mentioned

 

[Eric]

Amen!!!

 

[Kumar]

Please no time to submit and read its REAL TRUTH.

 

[learnfpga]

I am new to FPGA and VHDL too but as far as I know in ISE Webpack 7.1
there is something called language templates and in there you can find
code for all the basic logic circuits.

I totally agree with Srini about learning it yourself so hopefully next
time you will not come to this group to be spoonfed.

 

[Kumar]

O really sorry!!
Please tell me exact link for that I was not able to find it ISE
Webpack 7.1 language templates!!!

I will not come in this group next time and I wil learn things on
myself!!!


Please tell me the link!!

Sorry once again

 

[Srinivasan Venkataramanan]

Kumar,
Sorry to see your rush into "some how solve problem of today" (and
think about next one when it comes). It is almost 3 days since your original
post and it certainly doesn't take 3 days for one to write a counter in
VHDL. Nevertheless here is some pseudo-code, now DOIT yourself. You've asked
for UPDOWN counter:

if (up) cnt += 1;
if (down) cnt -= 1;

Disclaimer: No guarantee that this is a VHDL code (it is NOT)
No guarantee that such operators (+=, -=) exist in VHDL.
Logic is incomplete as well.

If you display similar attitude in industry - saying "some how let me get
this chip/block done by an online forum", and I will learn how to do it next
time around - be assured: you will be fired from the job. I hope you are
studying to get a job at the end of the day!

Good luck
Srini

--
Srinivasan Venkataramanan
Co-Author: SystemVerilog Assertions Handbook, http://www.abv-sva.org
Co-Author: Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition.
http://www.noveldv.com
I own my words and not my employer, unless specifically mentioned

 

[Eric]

Kumar,

Most people in this group are very willing to help fix / solve
problems. That is what engineers do!!!

But you have show that you have made an honest effort first.

We'll help you fix your work, but not do your work for you.

Eric

 

[learnfpga]

Hello Guys,
This guy Kumar is beyond help and I feel he does disservice to forums
like these where people come to look for help. He wants free
lunches...........BY THE WAY KUMAR EVEN FREE LUNCHED NEED TO BE CHEWED
AND DIGESTED BY YOU AND YOU ONLY.

I am pissed at him because I came across some of his recent stupid
questions in other newsgroups.

 

[Andy Peters]

Please no time to submit and read its REAL TRUTH.

Wise man once say:

"Lack of proper planning on your part does not constitute emergency on
my part."

-a

 

[james]

+<O really sorry!!
+<Please tell me exact link for that I was not able to find it ISE
+<Webpack 7.1 language templates!!!
+<
+<I will not come in this group next time and I wil learn things on
+<myself!!!
+<
+<
+<Please tell me the link!!
+<
+<Sorry once again

******

When you open Webpack Project Navagator or ISE Project Navagator, look
at the icon bar at the top. to the far left will be a lightbulb
symbol. Click on it and the Language template help will appear within
the project navagator.

have fun

james