S
Shannon
Ok, I know how latches can be inferred from missing assignments. Here
is what I have:
process(clk, reset)
begin
if reset = '1' then
...
x < = '0';
...
elsif rising_edge clk then
x <= '0';
case state is
when....
when....
when....
if something then
x <= '1';
elsif something_else then
....
else
....
end if;
end case;
end if;
end process;
why is 'x' a latch?
Shannon
is what I have:
process(clk, reset)
begin
if reset = '1' then
...
x < = '0';
...
elsif rising_edge clk then
x <= '0';
case state is
when....
when....
when....
if something then
x <= '1';
elsif something_else then
....
else
....
end if;
end case;
end if;
end process;
why is 'x' a latch?
Shannon