R
Reply7471859353
Note: The context save does not use the return stack, of current.
Context information ( X/Y/RETURN POP, ) and status state is saved into
a status register stack with a maskable exit_status instruction.
maw
Context information ( X/Y/RETURN POP, ) and status state is saved into
a status register stack with a maskable exit_status instruction.
maw
REV 3-8-2002
---
16-bit 1.109b by Mark A. Washburn
email: (e-mail address removed) or (e-mail address removed)
7 Isanti Estates #13
Isanti MN 55040
--------------------------------------------------------------------
16-bit fault tolerant instruction decode proposal for IBM Department of
Defense
--------------------------------------------------------------------
16-bit instruction decode ( IP)
16-bit instruction decodes align every four decodes ( IP) ( 2 or 3
branch balance) ( for performance ... )
data cell size is 32-bit ( 16-bit half, 64-bit double)
SMP 16 (64) MPP 16
--------------------------------------------------------------------
( type 1): VLIW-1 // hardware cache load length instruction
0 0 0 0 X X X X X X X X X X X X
Where X X X X X X X X X X X X is a CPU instruction cache pre-fetch
count of 1 to 4095 instruction words. TYPE SAFTEY: If X = 0 ( zero)
then return illegal instruction error.
( type 2): BRANCH-RELATIVE // polynominal degree 0 flow control
0 0 1 0 X X X X X X X X X X X X
Where X X X X X X X X X X X X is a data literal with a value between
-2048 thru 2047 that is subtracted to decrement the instruction pointer
for branching the instruction pointer ( hardware IP register).
( type 3): IF-ZERO-BRANCH-RELATIVE ( s0) - - ( ) // polynominal
degree 0 flow control
0 0 1 1 X X X X X X X X X X X X
Where X X X X X X X X X X X X is a data literal with a value between
-2048 thru 2047 that is added if top-of-stack compare equals ZERO
condition then add the data literal with the instruction pointer for
branching the instruction pointer ( hardware IP register).
( type 4): PRIMITIVE // primitive sub-decode
0 1 0 0 X X X X X X X X X X X X
Where X X X X X X X X X X X X encodes a processor instruction primitive
( with a maximum of 4095 possible medium size computer instruction code
types). If X = 0 ( zero) then return illegal instruction error.
( type 5): CALL-RELATIVE // polynominal degree 1 flow control
0 1 0 1 X X X X X X X X X X X X
Where X X X X X X X X X X X X is a data literal with a value between
-2048 and 2047 that is subtracted from the current instruction pointer
after the current instruction pointer plus one is saved in the RETURN
stack. If a corresponding EXIT instruction is decoded, the hardware
context register(s) will be restored to it's saved state and execution
will continue with the next full instruction decode. If X = 0 ( zero)
then return illegal instruction error.
( type 6): IF-POSITIVE-BRANCH-RELATIVE ( s0) - - ( ) // polynominal
degree 0 flow control
0 1 1 0 X X X X X X X X X X X X
Where X X X X X X X X X X X X is a data literal with a value between
-2048 thru 2047 that is added if top-of-stack compare equals POSITIVE
integer condition then add the data literal with the instruction
pointer for branching the instruction pointer ( hardware IP register).
( type 7): PERFORM-CLASS-BASE-METHOD // polynom. degree 2 flow
control
0 1 1 1 X X X X X X X X X X X X
Where X X X X X X X X X X X X is a data literal with a value between 0
and 4095 that indexes a table of CLASS-BASE-REGISTER register indirect
subroutine addresses. The current instruction pointer plus one is
saved in the RETURN stack. When the indirect call is executed and a
corresponding EXIT instruction decode is performed, the hardware IP
register will be restored to it's saved state and execution will
continue with the next full instruction decode. If X = 0 ( zero) then
return TYPE SAFETY CLASS-BASE-REGISTER fault.
CLASS LOCAL METHODS register & CLASS BASE MTHODS register
-- indexed indirect call for high level language compiler, dynamic
linking
-- if seperated from class local methods then could be *locked* in VLIW
cache; whereas, if overlaid on same register protection is complicated.
( type 8): VLIW-0 // CAM mapping
1 X X X X X Y Y Y Y Y Z Z Z Z Z
PACKED CODE TYPE SAFTEY: if X X X X X equals 1 1 1 1 1 then return
illegal instruction error or permit 16-but use mode switch.
-- 5 bit on 16-bit boundary should be adequate
with 5 bits for 64-bit wide relative branches for most nested coding
-- or 7 bit on 64-bit boundary ... only 9 per 64-bit data element
however
larger literal size
-- could also trigger wired taxonomy
--------------------------------------------------------------------
( type 4: sub-decode(s))
NOP ( ) - - ( ) // NO OPERATION
SWAP ( s0 s1) - - ( s1 s0)
DUP ( s0) - - ( s0 s0) // DUPLICATE
ROT ( s0 s1 s2) - - ( s1 s2 s0) // ROTATE
OVER ( s0 s1) - - ( s0 s1 s0)
FETCH ( s1) - - ( s0)
STORE ( s0 s1) - - ( )
DROP ( s0) - - ( )
FETCH-LOCAL-VARIABLE ( s0:[1..32]) - - ( s1) // where
literal value of [1..32] may be inline decoded
STORE-LOCAL-VARIABLE ( s1 s0:[1..32]) - - ( )
FETCH-TOS-INDIRECT ( s0:[1..32]) - - ( s1) // where -1
equals OVER
*** Feb 28, 2002 -- [1..16] maybe an acceptable limit to the on-chip
stack optimized version of "PICK" -- excusing myself of "statistical
certainty" ...
complexity numbers I use are 3 to 7 general maximum, with up to 15 rare
maximum ...
STORE-TOS-INDIRECT ( s1 s0:[1..32]) - - ( )
...
-- FETCH-CS-INDIRECT
-- STORE-CS-INDIRECT
PERFORM-CLASS-LOCAL-METHOD ( s0:[1..32]) - - ( ) // where
literal value of [1..32] may be inline decoded
PERFORM-CLASS-BASE-METHOD ( s0:[1..4096]) - - ( ) // repeated
here for consistancy, see type 7.
SWAP-X-WITH-Y
POP-TOS-TO-X ( s0) - - ( )
PUSH-X-TO-TOS ( ) - - ( s1) // X value is saved (
non-destructive)
SWAP-TOS-WITH-X ( s0) - - ( s1)
ADD-UNSIGNED-TO-X ( s0) - - ( )
ADD-SIGNED-TO-X ( s0) - - ( ) // add signed with unsigned
X
ADD-UNSIGNED-ONE-TO-X
ADD-UNSIGNED-TWO-TO-X
POP-TOS-TO-Y ( s0) - - ( )
PUSH-Y-TO-TOS ( ) - - ( s1) // Y value is saved (
non-destructive)
SWAP-TOS-WITH-Y ( s0) - - ( s1)
ADD-UNSIGNED-TO-Y ( s0) - - ( )
ADD-SIGNED-TO-Y ( s1) - - ( ) // add signed with unsigned
Y
ADD-UNSIGNED-ONE-TO-Y
ADD-UNSIGNED-TWO-TO-Y
ADD-UNSIGNED ( s1 s0) - - ( s2)
ADD-SIGNED ( s1 s0) - - ( s2)
ADD-SIGNED-WITH-CARRY ( s1 s0) - - ( s2)
SUB-UNSIGNED ( s1 s0) - - ( s2)
SUB-SIGNED ( s1 s0) - - ( s2)
SUB-SIGNED-WITH-CARRY ( s1 s0) - - ( s2)
MULTIPLY-UNSIGNED
MULTIPLY-SIGNED
MULTIPLY/DIVIDE-SIGNED
DIVIDE-SIGNED
DIVIDE/MODULO-SIGNED
AND // logical AND
OR // logical OR
XOR // logical Exclusive-OR
EQV // logical Equivalence
IMP // logical Implication
NOT // XOR with minus one ( -1)
BIT-CLEAR ( s0 s1) - - ( s2) // where s1 is BIT-CLEAR mask
* Use logical OR to perform a BIT-SET
ABSOLUTE // twos complement
NEGATE // twos complement
MINIMUM
MAXIMUM
LOGICAL-SHIFT-LEFT ( s0) - - ( s1)
LOGICAL-SHIFT-RIGHT ( s0) - - ( s1)
ARITHMETIC-SHIFT-RIGHT ( s0) - - ( s1) // copies carry into sign
( high) bit
LOGICAL-SHIFT-LEFT ( s1 s0:[1..32]) - - ( s3)
LOGICAL-SHIFT-RIGHT ( s1 s0:[1..32]) - - ( s3)
ARITHMETIC-SHIFT-RIGHT ( s1 s0:[1..32]) - - ( s3) // copies carry
into sign ( high) bit
ROTATE-LEFT-THRU-CARRY
ROTATE-RIGHT-THRU-CARRY
ROTATE-LEFT
ROTATE-RIGHT
PUSH-LITERAL-16-BIT-NEGATIVE ( ) - - ( s0)
PUSH-LITERAL-16-BIT-POSITIVE ( ) - - ( s0)
PUSH-LITERAL-32-BIT ( ) - - ( s0)
ALLOT ( s0) - - ( s1) // see note ***
ALLOT-LITERAL-COUNT [1..65536] ( ) - - ( s1) // see note ***
*** s1 is address where s0 cells where ALLOTed
COMPARE-SIGNED ( s0 s1) - - ( s2:[0,1,-1])
COMPARE-UNSIGNED ( s0 s1) - - ( s2:[0,1,-1])
EXIT
EXIT-IF-TOS-NON-ZERO
EXIT-IF-TOS-ZERO
EXIT-IF-TOS-NEGATIVE
EXIT-IF-TOS-POSITIVE
EXIT-IF-CARRY-TRUE
EXIT-IF-CARRY-FALSE
-- note re: PUSH/POP context where context is stack machine registers
that
maybe saved with single instruction in various combinations ei XY-SAVE
or XY-LOCAL-SAVE setting possibly EXIT -- not certain about best way to
implement an -- maybe two types of exits where one type pops a flags
register from return stack then restores the state
(x,y,local-static,local-methods, ...) before restoring IP ...
mirroring by similar context save X or XY or XY-local-static with state
restore flag, seperated from processor zero,overflow,sign flags:
return stack maps:
context-restore-flags
( optional: condition-flag x-register y-register local-static
local-methods ) return-address
SKIP-WORDS-FORWARD-IF-CARRY-TRUE [1..65536]
SKIP-WORDS-FORWARD-IF-CARRY-FALSE [1..65536]
( ) - - ( )
SKIP-WORDS-FORWARD-IF-TOS-NON-ZERO [1..65536]
SKIP-WORDS-FORWARD-IF-TOS-ZERO [1..65536]
SKIP-WORDS-FORWARD-IF-TOS-NEGATIVE [1..65536] // Test of bit 32
SKIP-WORDS-FORWARD-IF-TOS-POSITIVE [1..65536] // Test of bit 32
( s0) - - ( )
SKIP-WORDS-FORWARD-IF-COMPARE-EQUAL [1..65536]
SKIP-WORDS-FORWARD-IF-COMPARE-LESS [1..65536]
SKIP-WORDS-FORWARD-IF-COMPARE-LESS-OR-EQUAL [1..65536]
SKIP-WORDS-FORWARD-IF-COMPARE-GREATER [1..65536]
SKIP-WORDS-FORWARD-IF-COMPARE-GREATER-OR-EQUAL [1..65536]
( s0 s1) - - ( )
SKIP-WORDS-BACKWARD-IF-CARRY-TRUE [-65536..-1]
SKIP-WORDS-BACKWARD-IF-CARRY-FALSE [-65536..-1]
( ) - - ( )
SKIP-WORDS-BACKWARD-IF-TOS-NON-ZERO [-65536..-1]
SKIP-WORDS-BACKWARD-IF-TOS-ZERO [-65536..-1]
SKIP-WORDS-BACKWARD-IF-TOS-NEGATIVE [-65536..-1] // Test of bit
32
SKIP-WORDS-BACKWARD-IF-TOS-POSITIVE [-65536..-1] // Test of bit
32
( s0) - - ( )
SKIP-WORDS-BACKWARD-IF-COMPARE-EQUAL [-65536..-1]
SKIP-WORDS-BACKWARD-IF-COMPARE-LESS [-65536..-1]
SKIP-WORDS-BACKWARD-IF-COMPARE-LESS-OR-EQUAL [-65536..-1]
SKIP-WORDS-BACKWARD-IF-COMPARE-GREATER [-65536..-1]
SKIP-WORDS-BACKWARD-IF-COMPARE-GREATER-OR-EQUAL [-65536..-1]
( s0 s1) - - ( )
--------------------------------------------------------------------
* bus commands might also be an inline literal type with an inline
device-id and address literal
* bus commands may be BLOCKED or UNBLOCKED
* bus command data and instruction addresses are protected by ( within
control of) a highest priority stack process ( of 16 stacks) (
reference: memory protection types)
* memory address protection violation errors are trapped thru highest
stack priority.
* bus data transfers are first negotiated thru highest stack priority.
* bus data bandwidth is allocated on a per stack basis thru highest
stack priority.
* highest stack priority is first stack to interlock bus on boot,
priority decreases thru remaining stacks to interlock bus.
SUPER-BUS-CALL ( WHERE device id ( [0..15]:[0..15][0..3]) zero is super
space context, device state data mapping control (
bus-processor-index:[bus-processor-stack-index][fault-tolerant-index])
)
( device-id call-address) - - ( s0:[0:OK,-1:error])
SUPER-BUS-READ-SINGLE
( device-id data-address) - - ( s1:data-literal
s0:[0:OK,-1:error])
SUPER-BUS-WRITE-SINGLE
( s1:data-literal device-id data-address) - - (
s0:[0:OK,-1:error])
SUPER-BUS-READ-DOUBLE
( device-id data-address) - - ( s2:data-literal s1:data-literal
s0:[0:OK,-1:error])
SUPER-BUS-WRITE-DOUBLE
( s2:data-literal s1:data-literal device-id data-address) - - (
s0:[0:OK,-1:error])
SUPER-BUS-READ-TRANSFER
( data-literal-transfer-length from-local-address
to-super-address device-id) - - ( s0:[0:OK,-1:error])
SUPER-BUS-WRITE-TRANSFER
( data-literal-transfer-length to-local-address
from-super-address device-id) - - ( s0:[0:OK,-1:error])
SUPER-BUS-READ-PROCESSOR-STATUS-FLAGS ( BLOCKED:volatile)
( device-id ) - - ( s1:data-literal s0:[0:OK,-1:error])
SUPER-BUS-WRITE-PROCESSOR-STATUS-FLAGS ( BLOCKED:volatile)
( s0:status-literal device-id ) - - ( s0:[0:OK,-1:error])
SUPER-BUS-WRITE-PROCESSOR-CONTROL-WORD ( BLOCKED:volatile)
( s1:command-literal device-id ) - - ( s0:[0:OK,-1:error])
SUPER-BUS-ATTACH-PROCESSOR-STATUS-CONTROL-PORT-BASE-ADDRESS
( device-id ) - - ( s1:data-literal s0:[0:OK,-1:error])
DEVICE-BUS-CALL ( WHERE device id zero is self ( [0..15]:[0..15][0..3])
( device-id call-address) - - ( s0:[0:OK,-1:error])
DEVICE-BUS-READ-SINGLE
( device-id data-address) - - ( s1:data-literal
s0:[0:OK,-1:error])
DEVICE-BUS-WRITE-SINGLE
( s1:data-literal device-id data-address) - - (
s0:[0:OK,-1:error])
DEVICE-BUS-READ-DOUBLE
( device-id data-address) - - ( s2:data-literal s1:data-literal
s0:[0:OK,-1:error])
DEVICE-BUS-WRITE-DOUBLE
( s2:data-literal s1:data-literal device-id data-address) - - (
s0:[0:OK,-1:error])
DEVICE-BUS-READ-TRANSFER
( data-literal-transfer-length from-local-address
to-device-address device-id) - - ( s0:[0:OK,-1:error])
DEVICE-BUS-WRITE-TRANSFER
( data-literal-transfer-length to-local-address
from-device-address device-id) - - ( s0:[0:OK,-1:error])
DEVICE-BUS-READ-PROCESSOR-STATUS-FLAGS ( BLOCKED:volatile)
( device-id ) - - ( s1:data-literal s0:[0:OK,-1:error])
DEVICE-BUS-WRITE-PROCESSOR-STATUS-FLAGS ( BLOCKED:volatile)
( s0:status-literal device-id ) - - ( s0:[0:OK,-1:error])
DEVICE-BUS-WRITE-PROCESSOR-CONTROL-WORD ( BLOCKED:volatile)
( s1:command-literal device-id ) - - ( s0:[0:OK,-1:error])
DEVICE-BUS-ATTACH-PROCESSOR-STATUS-CONTROL-PORT-BASE-ADDRESS
( device-id ) - - ( s1:data-literal s0:[0:OK,-1:error])
--------------------------------------------------------------------
-- Set EXIT context restore flags ( restoring context registers from
return stack) ( EXIT-CONTEXT-BASE EXIT-CONTEXT-FLAGS WRITE-CONTROL-PORT
)
-- STATUSSIG_ALIVE SIG_PORT_BASE SIG_WATCHDOG
SIG_SOFT_RESET SIG_PORT_READ_ONLY_PROTECT_MASK
SIG_ADDRESS_REQUEST SIG_ADDRESS_READY SIG_ADDRESS_RETRY
SIG_BLOCK_REQUEST SIG_BLOCK_READY
SIG_BLOCK_WRITE SIG_BLOCK_READ SIG_DEADLOCK )
( ANY SIG_WATCHDOG CLEAR SIGNAL OR SIG_PORT_BASE CLEAR
SIGNAL
SETS SIG_PORT_READ_ONLY_PROTECT_MASK CLEAR )
( any fault:[super<-self<-device] )
-- COMMAND
CMD_PORT_READ_ONLY_PROTECT_MASK
CMD_READ_32 CMD_WRITE_32 CMD_READ_64 CMD_WRITE_64
CMD_ADDRESS_REQUEST CMD_BLOCK_REQUEST
CMD_WRITE_ADDRESS CMD_READ_BLOCK CMD_WRITE_BLOCK )
( SIG_SOFT_RESET ONLY SET THRU PROCESSOR STACK CONTROL
PROGRAM POSSIBLY USING BI-DIRECTIONAL CRC VERIFY,
BOOT CRC METHOD:0,FINAL CLOSURE
CRC:N,SIG_SOFT_RESET:0..N )
( ONLY BUS COMMANDS ALLOWED TO CHANGE PROCESSOR STATE
AFTER SIG_PORT_READ_ONLY IS SET ( WITH PROCESSOR
INTERNAL
DATA MEMORY PROTECTION FOR:[32,64,BLOCK or VARIABLE] )
)
-- X-REGISTER // internal register
-- Y-REGISTER // internal register
-- LOCAL-VARIABLES-REGISTER // indirect memory pointer
-- CLASS-LOCAL-METHOD-REGISTER // indirect memory pointer
-- CLASS-BASE-METHOD-REGISTER // indirect memory pointer
-- PARAMETER-STACK-REGISTER // indirect memory pointer
-- RETURN-STACK-REGISTER // indirect memory pointer
-- PORT_READ_ONLY_PROTECT_MASK
-- NEXT-ADDRESS
-- DMA-BLOCK-I/O-BASE
-- PACKED-CODE-MAP-REGISTERS // 16-bits each for [2-32]
-- PACKED-CODE-MAP-REGISTERS // thirty-one ( 31) internal CAM
registers for VLIW:0 type safety
-- INTERNAL-CONTROL-PORT-BASE-ADDRESS-REGISTER
* points to start of sixty-four ( 64) chip control ports (
1024-bits wide each)
* each fault tolerant stack is one control port followed by three
fault-tolerant backups ( green, yellow, red, N/S )
PUSH-INSTRUCTION-POINTER-REGISTER
POP-INSTRUCTION-POINTER-REGISTER // INDIRECT-GOTO
* stack memory protection violation errors are trapped thru highest
priority stack.
PUSH-PROCESSOR-FLAGS-REGISTER
POP-PROCESSOR-FLAGS-REGISTER
PUSH-RETURN-STACK-VALUE-TO-TOP-OF-PARAMETER-STACK
PUSH-TOP-OF-PARAMETER-STACK-VALUE-TO-RETURN-STACK
PUSH-PARAMETER-STACK-REGISTER
POP-PARAMETER-STACK-REGISTER
PUSH-RETURN-STACK-REGISTER
POP-RETURN-STACK-REGISTER
PUSH-LOCAL-VARIABLES-REGISTER // base vector for 32 indirect
storage
POP-LOCAL-VARIABLES-REGISTER // base vector for 32 indirect
storage
PUSH-CLASS-LOCAL-METHOD-REGISTER // base vector for 32 indirect
vectors
POP-CLASS-LOCAL-METHOD-REGISTER // base vector for 32 indirect
vectors
PUSH-CLASS-BASE-METHOD-REGISTER // base vector for 4096 indirect
vectors
POP-CLASS-BASE-METHOD-REGISTER // base vector for 4096 indirect
vectors
LOCK-CACHE // stack cache protect method
UNLOCK-CACHE // stack cache protect method
* the above two functions control hardware protected data cache
BLOCKED-MODE-OFF // continue stack processing after a bus command
BLOCKED-MODE-ON // pause stack processing after a bus command
UNBLOCK-SINGLE-WORD // continue stack processing after next bus cmd.
BLOCK-SINGLE-WORD // pause stack processing for next bus cmd.
--------------------------------------------------------------------
( maw note needs update for c.l.f. "The Answer to 'What is Forth'" )
..
EXIT
EXIT-IF-TOS-NON-ZERO
EXIT-IF-TOS-ZERO
EXIT-IF-TOS-NEGATIVE
EXIT-IF-TOS-POSITIVE
EXIT-IF-CARRY-TRUE
EXIT-IF-CARRY-FALSE
EXITF
EXITF-IF-TOS-NON-ZERO
EXITF-IF-TOS-ZERO
EXITF-IF-TOS-NEGATIVE
EXITF-IF-TOS-POSITIVE
EXITF-IF-CARRY-TRUE
EXITF-IF-CARRY-FALSE
Where EXITF instruction types,
1) first pop a context restore flag from the return stack,
2) check flags for X,Y,LOCAL-BASE, and/or BASE register stack
unnest(s),
3) performs processor state flags retore,
4) performs EXIT.
A pop of the context from the return stack both restores system state
flags and
may also trigger pop of X,Y,LOCAL-BASE, and/or BASE register stacks.
Intel --> 2.0
ARM --> 1.5
SMP MPP FORTH --> 1.0
SMP MPP FORTH VLIW is a sixteen parallel processor design that is
called
a single CPU. ( sixteen enhanced stack machine micro engines on a
single-chip/or/logical-cpu using a dual-buss architecture for super
scalability and providing a much greater theoretical fabrication
efficiency than IBM/Intel)
The IBM Defense version uses quad redundant CPUs for a single logical
CPU.
Whereas a non-fault tolerant CPU is either A) a single segment momory
or B) an
IBM like architecture using sixteen memories for a single CPU.
Fualt tolerance includes additional bus state signals and the memory
requirement for a single CPU is multiplied times four. (
RED/YELLOW/GREEN)
The maximum dual bus bandwidth will of course will vary greatly
depending
upon final fabrication constants. ( room temperaturl v.s. super
cooled, etc. )