latches again

[Tomas]

Hi,

I'm implementing a very simple memory with serial input in vhdl.

The serial bus I use is a simple SPI: I first receive the instruction
(read,write,erase) then the address then I send/receive data.

But I'm having some latches warning I would like to remove.

I'm using a FSM to model the memory, here is part of the code:


FSM: process (STATE)
variable TMP_RECV_INST:std_logic_vector(7 downto 0);
variable TMP_RECV_ADDR:std_logic_vector(15 downto 0);
variable TMP_RECV_DATA:std_logic_vector(7 downto 0);

begin
NEXTSTATE<=STATE;
case STATE is
when FS_RECV_INST => if curr_indx/=inst_length-1 then
TMP_RECV_INST(curr_indx):=SI; -- SI is the serial input
curr_indx:=curr_indx+1;
NEXTSTATE<=FS_RECV_INST;
else
curr_indx:=0;
NEXTSTATE<=FS_RECV_ADDR;
end if ;
SO<='Z';
when FS_RECV_ADDR => if curr_indx/=addr_length then
and so on

I'm getting a 1-bit latches warning on each tmp_recv_inst index
(because I'm probably changing only 1 bit at a time?). I even tried to
put TMP_RECV_INST(curr_indx):=SI; before the beginning of the if
clause just to test and see if the problem was that tmp_recv_inst
wasn't assigned in both if and else blocks. But the warning was still
there.

The only way I could think about to avoid this latches warning is
this:

change
variable TMP_RECV_INST:std_logic_vector(7 downto 0); to variable
tmp_recv_inst: integer range 0 to 2**7;

and instead of TMP_RECV_INST(curr_indx):=SI; use
tmp_recv_inst=tmp_recv_inst+2**curr_indx;

I'm a real VHDL beginner so I don't know if this *workaround* is
usable and what are the pros and cons.

Thanks for help,
Tomas

 

[Ralf Hildebrandt]

But I'm having some latches warning I would like to remove.

Ask yourself:
Does the target architecture support latches?
Does your guidelines for this project allow to use latches?
Did you model a latch?

...
I'm getting a 1-bit latches warning on each tmp_recv_inst index
(because I'm probably changing only 1 bit at a time?).

No. A latch is

process(enable)
begin
if (enable='1') then
my_latch<=my_input;
end if;
end process;

In contrast if you model pure combinational logic the signal you write
to has to be assigned a value in every case e.g.

process(enable)
begin
if (enable='1') then
my_output<=my_input;
else
my_output<='0';
end if;
end process;

This means: Somewhere in your case statement there is (at least) one
case of choice, that is not covered.
A latch warning is given by some synthesis tools, because you may have
forgotten one case of choice and the combinational logic you wanted to
bodel became a latch.

The only way I could think about to avoid this latches warning is
this:
...
I'm a real VHDL beginner so I don't know if this *workaround* is
usable and what are the pros and cons.

Do not "avoid latch waningings". Threat them as
* eigther an error report, because there is a latch where no latch was
modeled
* or as a not-so-useful information that there is a latch where you did
model one

Try to model hardware with VHDL - do not "program VHDL". You should know
everytime what will be inferred. This is not hard, because there are
only 3 choices: combinational logic, latch or flipflop.



And last of all: Latches are really nice, but hard to implement because
of some problems that arise while using them (e.g. muxed latch problem).
In most cases a fully synchronous design is preferrable (only comb.
logic and flipflops).

Ralf