I know the topic of latches is repeated again and again and again but there's one thing I don't know how to get around.
Below is a part of my code. It's one of the states in a state machine that serially shifts out bits in an asynchronous FIFO with parallel input and serial output. There is no signal telling the FIFO to spit the data out. It just starts shifting out whenever there is something in the FIFO.
This state generates an output clock signal 'sck' that is defined as a variable inside this state machine process. Xilix ISE reports a warning that a latch is inferred here, which is rather obvious since that is exactly what I need - to keep the value of sck until the clk_count signal reaches a certain value when I want to invert the sck value. I also get a 16-bit latch for send_shift_reg as I only update its contents on every falling edge of 'sck'. Why is that wrong?
The question really is is this an OK way of writing this? If no, then why and how to do it differently? (Assuming that I really need the sck to be a variable in the process)
The same happens here with the FIFO_array signal only if I omit the 'else' condition. But if I leave it there isn't a latch inferred anyway? Isn't it just the ISE software that doesn't generate a warning?
Below is a part of my code. It's one of the states in a state machine that serially shifts out bits in an asynchronous FIFO with parallel input and serial output. There is no signal telling the FIFO to spit the data out. It just starts shifting out whenever there is something in the FIFO.
Code:
when SENDING =>
if (clk_countNow = SCK_PERIOD-1) then
Send_shift_reg := Send_shift_reg(14 downto 0) & '0';
sck := not sck;
if (bit_countNow = 15) then
bit_countNext <= 0;
sentNext <= '1';
else
bit_countNext <= bit_countNow + 1;
end if;
elsif (clk_countNow = (SCK_PERIOD/2 - 1)) then
sck := not sck;
end if;
if (clk_countNow = SCK_PERIOD-1) then
clk_countNext <= 0;
else
clk_countNext <= clk_countNow + 1;
end if;This state generates an output clock signal 'sck' that is defined as a variable inside this state machine process. Xilix ISE reports a warning that a latch is inferred here, which is rather obvious since that is exactly what I need - to keep the value of sck until the clk_count signal reaches a certain value when I want to invert the sck value. I also get a 16-bit latch for send_shift_reg as I only update its contents on every falling edge of 'sck'. Why is that wrong?
The question really is is this an OK way of writing this? If no, then why and how to do it differently? (Assuming that I really need the sck to be a variable in the process)
The same happens here with the FIFO_array signal only if I omit the 'else' condition. But if I leave it there isn't a latch inferred anyway? Isn't it just the ISE software that doesn't generate a warning?
Code:
writeprocess : process (value_in, value_ready, reset, full)
variable countNow, countPrev : integer range 0 to FIFO_MAX := 0;
begin
if (reset = '1') then
countNow := 0;
countPrev := 0;
WR_rollover <= '0';
FIFO_array <= (others => (others => '0'));
elsif (rising_edge(value_ready) and full = '0') then
countPrev := countNow;
FIFO_array(WR_countNow) <= value_in;
if (countNow = FIFO_MAX) then
countNow := 0;
WR_rollover <= not WR_rollover;
else
countNow := countNow + 1;
end if;
else
FIFO_array <= FIFO_array;
end if;
WR_countNow <= countNow;
WR_countPrev <= countPrev;
end process;