loop 10000 iterations limit in quartusII.

[Luis Cupido]

Hello,

I have a perfect working VHDL code that fills in a RAM
with sine sine and cosine tables.
All works just fine.

As soon as I wanted to generate 16K or 32K of tables, bang!
compilation aborts and Quartus says it exists loops after 10000 iterations.
The help at altera site says it is intentional to prevent (dumb) users
from infinite loops Furthermor they say if one wants more than 10000
iteration go break the loop into more loops below 10000 iterations !!!

How bizarre !!! couldn't it just issue a warning ?...
(even DOS asked "are you sure" on del *.*... how funny it would be to
see "you are deleting too much files, go delete one by one") Ahhgggg !!!


Anyone one knows a way to bypass this ?
I would hate to slice my beautiful loops. specially as the component
has its size passed up on generics.

Luis C.

 

[Jim Lewis]

Hi Luis,
This is an indication of something iterating on delta cycles. I am assuming that you are treating the RAM as a ROM and pre-filling it some how. It is likely that the pre-fill operation has a "wait for 0 ns ;" in it.

The group can give you more insight if you are willing to post your code.

In hardware, while delta cycles do not correspond directly to actual delaysin your circuit, after synthesis they will be roughly proportional to yourcircuit delays. As a result, if you have 10,000 delta cycles in your actual hardware, you are generally out of luck in creating logic of any reasonable speed.

Best Regards,
Jim

 

[Luis Cupido]

Tks. Jim.

It is indeed a ROM using RAM blocks and the loop is the fill in of the
ROM contents.

None of those loops actually synthesize into hardware they just generate
the memory initialization file, as expected. So quartus really
interpreted my coding correctly.
And all works beautifully if the loop size stays below 10000 iterations.

Here is the altera info:

"CAUSE: ... you specified a loop that does not terminate within 10,000
iterations. This message may occur because the loop's terminating
condition depends on a signal or non-constant variable. You may also
have forgotten to increment a variable in the loop's terminating
condition. To avoid an infinite loop or memory exhaustion, Quartus II
Integrated Synthesis prematurely terminated the synthesis of your design.
ACTION: Check the loop for errors or non-constant terminating
conditions. If you can guarantee that your loop will exit within 10,000
iterations, you can bypass this error by adding an explicit exit
statement that terminates the loop after N < 10,000 iterations. If your
loop should iterate more than 10,000 times, <<< you will need to factor
the loop into multiple loops with 10,000 or fewer iterations each.>>>"

Last sentence is killing me as it sounds too silly to be true !!!


Here is my loop:

impure function SinFillTab return rom_type is
variable cpt: integer:=0;
variable rom_tmp: rom_type;
begin
cpt := 0;
while (cpt < QUART) loop
rom_tmp(cpt) := to_signed(integer(real(AMP)*sin(
real(cpt)*2.0*MATH_PI/real(FULL) ) ), 16);
cpt := cpt + 1;
end loop;

return(rom_tmp);
end SinFillTab;

 

[Jim Lewis]

Hi Luis,
That indeed is a silly error. Surely an artifact of when ROMs were never that big - .

Did you try a nested pair of loops such as the following (minus any bugs I might have coded). It seems like a simple check that you might be able to work around to some degree.

impure function SinFillTab return rom_type is
variable cpt, IterationLimit : integer:=0;
variable rom_tmp: rom_type;
begin
cpt := 0;
OUTER : while (cpt < QUART) loop
IterationLimit := 1;
INNER : while (IterationLimit < 10,000 and cpt < QUART) loop
rom_tmp(cpt) := to_signed(integer(real(AMP)*sin(
real(cpt)*2.0*MATH_PI/real(FULL) ) ), 16);
cpt := cpt + 1;
IterationLimit := IterationLimit + 1 ;
end loop INNER ;
end loop OUTER ;
return(rom_tmp);
end SinFillTab;

Have you submitted a bug report to them? I would include your code so they know it is their silly issue and not yours.

Jim

 

[KJ]

It is indeed a ROM using RAM blocks and the loop is the fill in of the

ROM contents.

- Have you tried a for loop rather than a while loop? Maybe the checking for 10,000 is only done on 'while' loops since 'while' depend on a loop condition that the synthesizer needs to evaluate on each loop. A 'for' loop can be statically analyzed to determine exactly how many loops would be needed so there should be no reason for it to limit you there.
- As Jim mentioned, submit the case to Altera. Even if you're using the free tools and maybe not getting any actual support, it does at least send something into them about problems with their tools that they might decide tofix.
- When you submit to Altera, might also ask if there is any way to modify that 10,000 limit so that you can work around this limitation in their tool.

Kevin Jennings

 

[Luis Cupido]

- Have you tried a for loop rather than a while loop?

Thanks for the hint.
indeed It WORKS fine with a "for loop".

Okay... I can understand their reasons... even so I would prefer to be the
the one that make infinite loops occasionally rather then be restricted
from writing code freely.
IMHO this would be a very good case for a warning and not for a show
stopper.
if one suspected that the compiler is taking too long would see the
warning and decide to abort or let it continue.

impure function SinFillTab return rom_type is
variable cpt: integer:=0;
variable rom_tmp: rom_type;
begin

for cpt in 0 to QUART-1 loop
rom_tmp(cpt) := to_signed(integer(real(AMP)*sin(
real(cpt)*2.0*MATH_PI/real(FULL) ) ), 16);
end loop;

return(rom_tmp);
end SinFillTab;

 

[Daniel Kho]

- When you submit to Altera, might also ask if there is any way to modifythat 10,000 limit so that you can work around this limitation in their tool.

This reminds me of a case I filed to Altera a long time ago. I remember ModelSim giving me an "iteration limit reached" error, but Quartus failed to give me any error at the time. For your case, seems like Quartus did finallygive an error when the iteration limit is reached.

The case I filed to Altera points to the fact that Quartus supports Verilogiteration limits, but not for VHDL. It didn't seem to make any sense that they could do for one language and ignore the other. Anyway, you got me checking back on this again.

I saw that there is no option for us to change the iteration limit (though the one for Verilog is still there):
Assignments > Settings > Analysis & Synthesis Settings > More Settings > Iteration limit for (non-)constant Verilog loops

Perhaps Altera is slowly supporting VHDL iteration limits, though the feature to change it away from 10,000 is not there yet.

As with others, I suggest you file a case with Altera.

-daniel