Matrix handling

[vedpsingh]

Below I am mentioned a program which is a part of a bigger system. The
program is very simple(don't be carried by the size of posting )
The requirement is that, based on input signal "InvertBit_x"
(x=0,1,...7) , a look-up has to be made in constant ALPHA.
when "InvertBit_X" matches ALPHA(k) than use this index 'k' to invert
the 'k'th bit in one row(here 1st) of Matrix "Uncorrect_Mat" and write
the entire Row in Matrix "CorrectedMatrixRow".
This process is to be done for all values of InverBit_x i.e. for all
Rows of the Matrix "Uncorrect_Mat" .
Here in program I am mentioning only for the 1st Row.
Problem is that , in this approach,at the row position where bit is
supposed to be inverted, I am getting a value 'X' , when process is
completed .
Please point out the problem. or if there is a better method do it !
(This is the first time I am handling a matrix like thing in FPGA, so I
am not very confident)
-------------------------------------------------------------------------------------------------------------------------
library WORK,IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use WORK.CONV.ALL;

entity Bit_InversionRow is

port(
Uncorrect_Mat : in MATRIX ; ---XORed Matrix ---> Uncorrected Matrix

clock,Reset: in std_logic;
--Based on these InverBit signal information, Matrix will be
corrected
InvertBit_0 : in std_logic_vector (7 downto 0);
InvertBit_1 : in std_logic_vector (7 downto 0);
InvertBit_2 : in std_logic_vector (7 downto 0);
InvertBit_3 : in std_logic_vector (7 downto 0);
InvertBit_4 : in std_logic_vector (7 downto 0);
InvertBit_5 : in std_logic_vector (7 downto 0);
InvertBit_6 : in std_logic_vector (7 downto 0);
InvertBit_7 : in std_logic_vector (7 downto 0);

CorrectedMatrixRow : out MATRIX
);
end Bit_InversionRow;

architecture BEHVBit_InversionRow of Bit_InversionRow is

constant alpha : alphaARRAY :=
(
0 => 1,
1 => 2,
2 => 4,
3 => 8,
4 => 3,
5 => 6,
6 => 12,
7 => 11,
8 => 5,
9 => 10,
10 => 7,
11 => 14,
12 => 15,
13 => 13,
14 => 9
) ;
----------
signal UncorrectMatrixSig : Matrix;
signal CorrectMatrixSig : Matrix;

begin
--------------------------------------------------------------------
UncorrectMatrixSig <= Uncorrect_Mat;
----------------------------------------------------------------

bitCorrect_row1 : process (Reset,InvertBit_1,clock)

variable STS : boolean ;
variable var_temp : integer range 0 to 15;
variable CorrectMatrixVar : MATRIX;
begin

if reset = '1' then
STS := FALSE;
var_temp := 0;

CorrectMatrixSig <= UncorrectMatrixSig ;

else
------------------Bit inversion-------------------
for k in 0 to N-2 loop ---N=16 in my case(defined in package)

if InvertBit_1 = 0 then
-----------------If InvertBit_1 is zero than there is no need to change
in row of matrix

CorrectMatrixSig(1,k) <= UncorrectMatrixSig(1,k);
else
STS := ( alpha(k) = InvertBit_1 ) ;
if STS = TRUE then
var_temp := (k) ;
CorrectMatrixSig(1,var_temp) <= not
(UncorrectMatrixSig(1,var_temp));
end if ;

end if ;

end loop;

end if ;

end process bitCorrect_row1;
---------------------------------------------------------
-----similarly repeat above process for all values of in put signal
InvertBit_x (wherex=2,3,4...7)

end BEHVHardQuantConst;

---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

----Packge used in above program is here:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
package CONV is
constant N : integer := 16 ; -- number of elements to sort
constant M : integer := 8 ; -- size of word to sort
constant A : integer := 3 ; --counter_length = Length of Vector
Matrix = 2^A

type MATRIX is array (0 to (2**A)-1 , 0 to N-1) of std_logic;
type alphaARRAY is array (0 to N-2) of integer range 0 to 15 ;
type TYPE_IO is array(0 to N-1) of std_logic_vector(M-1 downto 0);

end CONV;

--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Things were working fine when in one approach to debug I made the
"InvertBit_x" and Uncorrect_Mat CONSTANT, as mentioned below.

library WORK,IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use WORK.CONV.ALL;

entity Bit_InverTest is

port(
clock,Reset: in std_logic;
CorrectedMatrixRow : out MATRIX
);
end Bit_InverTest;

architecture BEHVBit_InverTest of Bit_InverTest is

constant alpha : alphaARRAY :=
(
0 => 1,
1 => 2,
2 => 4,
3 => 8,
4 => 3,
5 => 6,
6 => 12,
7 => 11,
8 => 5,
9 => 10,
10 => 7,
11 => 14,
12 => 15,
13 => 13,
14 => 9
) ;
----------
constant Uncorrect_Mat : MATRIX :=(

('1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1'),
('1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1'),
('1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1'),
('1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1'),
('1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1'),
('1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1'),
('1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1'),
('1','1','1','1','1','1','1','1','1','1','1','1','1','1','1','1')
);

------------
constant InvertBit_0 : integer :=5;
constant InvertBit_1 : integer :=8;
constant InvertBit_2 : integer :=1;
constant InvertBit_3 : integer :=14;
constant InvertBit_4 : integer :=11;
constant InvertBit_5 : integer :=7;
constant InvertBit_6 : integer :=9;
constant InvertBit_7 : integer :=12;

------------
signal UncorrectMatrixSig : Matrix;
signal CorrectMatrixSig : Matrix;

begin

--------------------------------------------------------------------
UncorrectMatrixSig <= Uncorrect_Mat;
----------------------------------------------------------------
bitCorrect_row1 : process (Reset,InvertBit_1 )

variable STS : boolean ;
variable var_temp : integer range 0 to 15;

begin

if reset = '1' then
STS := FALSE;
var_temp := 0;

CorrectMatrixSig <= UncorrectMatrixSig ;

else
------------------Bit inversion-------------------
for k in 0 to N-2 loop

if InvertBit_1 = 0 then
CorrectMatrixSig(1,k) <= UncorrectMatrixSig(1,k);
else
STS := ( alpha(k) = InvertBit_1 ) ;
if STS = TRUE then
var_temp := (k) ;
CorrectMatrixSig(1,var_temp) <= not
(UncorrectMatrixSig(1,var_temp));
end if ;

end if ;

end loop;

end if ;

end process bitCorrect_row1;

 

[Mike Treseler]

Problem is that , in this approach,at the row position where bit is
supposed to be inverted, I am getting a value 'X' , when process is
completed .

Perhaps the signal is driven by more than one process.

Please point out the problem. or if there is a better method do it !

Since you have a clock input, I suggest that
you use it to redo the problem as a single synchronous process.

-- Mike Treseler

 

[vedpsingh]

Perhaps the signal is driven by more than one process.


Since you have a clock input, I suggest that
you use it to redo the problem as a single synchronous process.

-- Mike Treseler

---------------------------------------------
Hi Mike,

I have made things clock dependent now (see code Below below), But it
didn't work !




bitCorrect_row1 : process (Reset,InvertBit_1,clock)

variable STS : boolean ;
variable var_temp : integer range 0 to 15;
variable CorrectMatrixVar : MATRIX;
begin
If Rising_Edge(clock) then
if reset = '1' then
STS := FALSE;
var_temp := 0;

CorrectMatrixSig <= UncorrectMatrixSig ;

elsif Rising_Edge(clock) then
------------------Bit inversion-------------------
for k in 0 to N-2 loop ---N=16 in my
case(defined in package)

if InvertBit_1 = 0 then
-----------------If InvertBit_1 is zero than there is no need to change
in row of matrix
CorrectMatrixSig(1,k) <=
UncorrectMatrixSig(1,k);
else
STS := ( alpha(k) =
InvertBit_1 ) ;
if STS = TRUE then
var_temp := (k) ;
CorrectMatrixSig(1,var_temp) <= not
(UncorrectMatrixSig(1,var_temp));
end if ;

end if ;

end loop;

end if ; ------end Reset
end if ; ----- end clock
end process bitCorrect_row1;