Memory Mapped Register Help

[KAY]

Hi,

I need help setting up memory mapped registers. I would like to latch data to these registers when data has been written to the memory locations. How would I write VHDL for this?

Thanks,
K

 

[KJ]

Hi, I need help setting up memory mapped registers. I would like to latch data to these registers when data has been written to the memory locations. How would I write VHDL for this? Thanks, K

entity foo is
Address: in natural range 0 to 255;
Write: in std_ulogic;
Write_data: in std_ulogic_vector(7 downto 0);
end foo;

architecture rtl of foo is
begin
process(clk)
begin
if rising_edge(clk) then
if (Write = '1') then
Mem(Address) <= Write_Data;
end if;
end if;
end process;
end rtl;

Kevin

 

[KAY]

entity foo is

Address: in natural range 0 to 255;

Write: in std_ulogic;

Write_data: in std_ulogic_vector(7 downto 0);

end foo;



architecture rtl of foo is

begin

process(clk)

begin

if rising_edge(clk) then

if (Write = '1') then

Mem(Address) <= Write_Data;

end if;

end if;

end process;

end rtl;



Kevin

Thanks so much for the reply,

Could you explain the line:
Mem(Address) <= Write_Data;

What is the Mem function? or am I just misunderstanding that line.

Thanks,
K

 

[KJ]

What is the Mem function? or am I just misunderstanding that line. Thanks, K

Sorry, missed a couple of lines...

Mem is a signal that is an array of the stuff that you want to store. Thiswould be defined inside the architecture like this...
architecture rtl of foo is
type t_My_Memory_Array is array(0 to 255) of std_ulogic_vector(Write_Data'range);
signal Mem: t_My_Memory_Array;
begin

Also, you don't say what you want to do with the data in the memory once ithas been written but presumably you would at least want to read it back addressed by the same address signal. That was not shown in the code either,but to implement that you would define a new output of the entity (I'll call it Read_Data) that is the same number of bits as 'Write_Data'. Then youadd the following line of code inside the 'if rising_edge' if statement, but outside the 'if Write='1'' statement as shown below

process(clk)
begin
if rising_edge(clk) then
if (Write = '1') then
Mem(Address) <= Write_Data;
end if;
Read_Data <= Mem(Address);
end if;
end process;

Kevin Jennings

 

[KAY]

Sorry, missed a couple of lines...



Mem is a signal that is an array of the stuff that you want to store. This would be defined inside the architecture like this...

architecture rtl of foo is

type t_My_Memory_Array is array(0 to 255) of std_ulogic_vector(Write_Data'range);

signal Mem: t_My_Memory_Array;

begin



Also, you don't say what you want to do with the data in the memory once it has been written but presumably you would at least want to read it back addressed by the same address signal. That was not shown in the code either, but to implement that you would define a new output of the entity (I'll call it Read_Data) that is the same number of bits as 'Write_Data'. Then you add the following line of code inside the 'if rising_edge' if statement,but outside the 'if Write='1'' statement as shown below



process(clk)

begin

if rising_edge(clk) then

if (Write = '1') then

Mem(Address) <= Write_Data;

end if;

Read_Data <= Mem(Address);

end if;

end process;



Kevin Jennings

Thank you so much! I will try to implement it