MIG(3.4) + Virtex(6) Clocking?

[TheProperNoun]

The component generated from using MIG needs two single-ended clocks,
sys_clk and clk_ref. I've come to understand that clk_ref needs to be
a 200MHZ clock and sys_clk should be the speed of my DDR3. As I'm
using an ML605 board I have a single 200MHZ differential clock coming
in. I use the clocking wizard to generate a component that produces
multiple single ended clocks. Unfortunately this wizard is limited; I
need to also generate a 125MHZ clock for Ethernet, but it won't allow
me to output a 125, 200, and 400MHZ clock (whichever clock I enter
third is always close, but not quite what I want, i.e. if I enter the
first two as 200 and 400, then under "actual" for the 125MZH clock it
says it runs at 120MHZ).

To get around this I tried to have the first clock manager generate a
125MHZ clock and a 200MHZ clock, and pass in the 200MHZ clock to a
second clock manager that outputs a 200 and 400MHZ clock, but
unfortunately I get an error that doesn't seem to make sense. Below
are the component declarations and instantiations of the two clock
managers, and then the error:

component CLKMNGR
port
(-- Clock in ports
CLK_IN1_P : in std_logic;
CLK_IN1_N : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
CLK_OUT3 : out std_logic;
-- Status and control signals
RESET : in std_logic
);
end component;

component CLKMNGRDDR3
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
CLK_OUT2 : out std_logic;
-- Status and control signals
RESET : in std_logic
);
end component;

CLKMNGR_inst : CLKMNGR
port map
(-- Clock in ports
CLK_IN1_P => REFCLK_P,
CLK_IN1_N => REFCLK_N,
-- Clock out ports
CLK_OUT1 => GTX_CLK, -- 125MHZ
CLK_OUT2 => REFCLK, -- 200MHZ Buffered
CLK_OUT3 => CLK200Out, -- 200MHZ Unbuffered
-- Status and control signals
RESET => reset_i );

CLKMNGRDDR3_inst : CLKMNGRDDR3
port map
(-- Clock in ports
CLK_IN1 => CLK200Out,
-- Clock out ports
CLK_OUT1 => CLK400UB,
CLK_OUT2 => CLK200UB,
-- Status and control signals
RESET => reset_i );

ERROR:NgdBuild:455 - logical net 'CLK200Out' has multiple driver(s):
pin CLKOUT2 on block CLKMNGR_inst/mmcm_adv_inst with type
MMCM_ADV,
pin PAD on block CLK200Out with type PAD

Now, CLK200Out is not connected to CLKOUT2, it's connected to
CLK_OUT3, and it's only driving one thing - CLKMNGRDDR3_inst. So I'm
completely confused as to what this error is really about. Does anyone
know what the cause of this error actually is, how to get this
working, or how I could generate a 125, 200, and 400 MHZ clock from a
single 200MHZ differential? Thanks.