Mixing different VHDL revisions between package and entity

[Sean Durkin]

Hi *,

it's taken me two days to find the problem here, and now I'm not sure if
what I'm observing is intended by the language or a ModelSim bug. Maybe
one of the gurus here can shed some light on this...

I was trying to do something simple (see code snippet below):
- Create a package file containing a bunch of procedures to simplify
signal generation in testbenches. The signals that should be updated in
the testbench are passed to the procedures as "signal" type parameters
- Create a testbench in a separate file that makes use of that package
and calls the procedures with the corresponding signals as parameters

Now what I did is compile the package file as VHDL-2002, and the
testbench file as VHDL-2008 (using "vcom -2002"/"vcom -2008", respectively).
When I run simulation, the signals that should be driven by the
procedures in the package are NOT updated. If I use VHDL-2008 for both
files, or VHDL-2002 for both files, or VHDL-2008 for the package and
VHDL-2002 for the testbench, everything works fine.

Is this a bug in Modelsim (I'm using 10.1b), or is this behaviour to be
expected because of some language change in VHDL-2008 that I'm not aware of?

Greetings,
Sean


Here's sample code I used to reproduce the problem:

First, the package file:

library ieee;
use ieee.std_logic_1164.all;

-- package declaration
package testcase_pack is
procedure drive_sig (signal sig_to_drive : out std_logic;
value : in std_logic);
end package testcase_pack;

-- package body
package body testcase_pack is

-- procedure that drives a signal
procedure drive_sig (signal sig_to_drive : out std_logic;
value : in std_logic) is
begin
sig_to_drive <= value;
end procedure drive_sig;

end package body testcase_pack;

Now, the testbench file:

library ieee;
use ieee.std_logic_1164.all;
use work.testcase_pack.all;

-- entity
entity testcase is
end entity testcase;

-- architecture
architecture behave of testcase is
signal signal_to_drive : std_logic;
begin
-- process that calls the procedure twice
call_proc: process is
begin
wait for 1 us;
drive_sig(signal_to_drive, '1');
wait for 1 us;
drive_sig(signal_to_drive, '0');
wait for 1 us;
assert (false) report "Simulation completed" severity failure;
end process call_proc;
end architecture behave;

 

[Sean Durkin]

Hi,

in case anyone's interested: seems to be a ModelSim bug.

Greetings,
Sean

 

[Paul Uiterlinden]

Hi,

in case anyone's interested: seems to be a ModelSim bug.

Thanks. I thought so (yeah I know: that's easy to say now).

From experience, what I know of mixing different VHDL language modes is that
you can mix them freely, as long as the secondary design unit
(architecture, package body) is compiled with the same mode as the primary
design unit (entity, package). If not, the compile will result in an error.

 

[Sean Durkin]

Hi Paul,

Thanks. I thought so (yeah I know: that's easy to say now).

From experience, what I know of mixing different VHDL language modes is that
you can mix them freely, as long as the secondary design unit
(architecture, package body) is compiled with the same mode as the primary
design unit (entity, package). If not, the compile will result in an error.

well, that I can understand. And an error or warning message sure
would've been helpful in finding the problem in my case.

I just switched to VHDL-2008 for my test bench because of some of the
"new" language features, and for the rest of the design I left
everything at the default (which for Modelsim 10 means compiling with
VHDL-2002). All of a sudden a previously prepared (and verified to be
working) package stopped working altogether, and of course I was at
first looking for errors in my design for a few hours...

Anyway, I reported it to Mentor, they can reproduce it and acknowledged
the bug, but I don't expect a fix anytime soon, since it's not a
critical issue. Simple to work around if you know about it...

Greetings,
Sean

 

[Sean Durkin]

Hi *,

I've been informed that this issue will be fixed in the upcoming
Modelsim release (I guess that would be 10.1c).