modeling connecting Processor with memory

[Pasacco]

dear

I implemented simple processor (actually simple FSM) -
- Input port: clock, reset, data_in
- Output prot: enable(memory enable), rw(read/write), address, data_out

And consider Memory (Xilinx BRAM) -
- Input port: EN, CLK, DI, RESET, WE, ADDR
- Output port: DO

Then I directly connected the processor with Memory, as follows.
- processor to Memory : enable => EN, rw => we, address => ADDR,
data_out => DI,
- memory to processor : DO => data_in
- clock and reset are all the same

Processor is working fine when the FSM (processor) is written as the
following.

Problem is that it is not working when the 'execution process below' is
rising edge clocked.

If someone has experience on this, let me know....

Thankyou in advance

---------------------------
architecture
begin
process(reset,clock) -- state transition process
begin
if reset='1' then
CS<=Init; -- current state
elsif clock'event and clock='1' then -- rising edge
NS<=CS; -- next state
end if;
end process;

process(CS,...)
begin
case ES is
when Init =>
if a='0' then NS <= READ_MEM1;
end if;
when READ_MEM1 =>
if b='1' then NS <= READ_MEM2;
end if;
.....
end case;
end process;

process (clock) -- execution process
begin
if clock'event and clock='0' then -- falling edge (ok)
-- if clock'event and clock='1' then -- rising edge (NOT ok)
case CS is
.....................
end case;
end if;
end process;
------------------------------------------------

 

[Mike Treseler]

Problem is that it is not working when the 'execution process below' is
rising edge clocked.

Consider running a simulation and looking
at the waveforms. Sounds like clock
and data are changing on the same tick.
Maybe you need a wait state.

-- Mike Treseler

 

[Pasacco]

Hi

That is correct that clock and data transit at the same time. Thankyou
for comment.

BTW, how is the coding style of the 3rd process in FSM above. 3rd
process is for combinational execution (generating output) block.

Is it okay to use falling edge clock in the process ?
Compared to non-clock or rising edge clock, what is advantage or
disadvantage ? Maybe falling edge clock in 3rd process is not a good
coding

Thankyou for anyone who comments

 

[Mike Treseler]

That is correct that clock and data transit at the same time. Thankyou
for comment.

You are welcome.

BTW, how is the coding style of the 3rd process in FSM above. 3rd
process is for combinational execution (generating output) block.

Consider combining everything into one clocked process.

Is it okay to use falling edge clock in the process ?

Your life will be simpler with one clock.
For FPGAs flops come free with the gates.
Might as well use them.

Compared to non-clock or rising edge clock, what is advantage or
disadvantage ? Maybe falling edge clock in 3rd process is not a good
coding

The advantage of using one clocked process is
that all outputs are automatically registered.
There is no internal wiring to worry about.
It just works, and you don't have to think so much.

-- Mike Treseler