modelling a FIFO in VHDL

[fpgawizz]

I am trying to send data via RS 232 to a spartan 3 development board that
has external SRAM. I want to send data to the RXD input of the FPGA and
have the FPGA send this to the SRAM. This is a simplex transmission from
my PC to the FPGA that is listening. Is there any models I can see or use
maybe for doing this kind of a UART, FIFO in VHDL ?

 

[Jezwold]

I assume that you have heard of the google search engine,well I suggest
you give that a try because i did and it worked for me.

 

[strada]

Would you please not spam forums with advice that is obvious. If they tried google and it brought them here, then your comment is not very useful. the point of a forum is to offer help, not criticism

 

[jeppe]

Well I believe this could be some of the informative you wants
http://www.jjmk.dk/MMMI/Lessons/07_Memory/No6_FIFObuffers/BRAM_based/index.htm

Besides - if your searching for PicoBlaze by Ken Chapman will you properly find an UART with built in FIFO buffers. If you cant find them let me know.

Your welcome
Jeppe

 

[vipinlal]

this may help you..
vhdlguru.blogspot.com/2010/03/basic-model-of-fifo-queue-in-vhdl.html