ModelSim Newbie , Need Help in Simulation

[KellyB]

Hi,

I'm new to testbenches so I set a goal to get some examples
to work under ModelSim PE Student Edition 6.4.

I'm trying to do the simplest of things - to simulate a vhdl file.
However once compiled, I have no objects hence nothing that can be added
to the waveform.

I get no errors at all, just no objects after I compile. I see the file
under my library, I can click on the testbench file and it opens
in SIM but objects window is simply empty.

Please Help !!!

 

[rickman]

Hi,

I'm new to testbenches so I set a goal to get some examples
to work under ModelSim PE Student Edition 6.4.

I'm trying to do the simplest of things - to simulate a vhdl file.
However once compiled, I have no objects hence nothing that can be added
to the waveform.

I get no errors at all, just no objects after I compile. I see the file
under my library, I can click on the testbench file and it opens
in SIM but objects window is simply empty.

I don't recall ModelSim exactly, but in ActiveHDL there is a view of
files and a separate view of the compiled entities. Can you see any
tabs for a different view or is there another window you can open?

Rick

 

[KellyB]

KellyB wrote: ...snip..


I don't recall ModelSim exactly, but in ActiveHDL there is a view of
files and a separate view of the compiled entities. Can you see any
tabs for a different view or is there another window you can open?

Rick

Thanks for the reply.
After some tinkering , i've managed to obtain the compiled objects but
now i have a different problem.

# Compile of test.v was successful.
vsim test.v
# vsim test.v
# ** Error: (vsim-19) Failed to access library 'test' at "test".
# No such file or directory. (errno = ENOENT)
# Error loading design



Can anyone using ModelSim Please help ?

 

[smqasim]

Thanks for the reply.
After some tinkering , i've managed to obtain the compiled objects but
now i have a different problem.

# Compile of test.v was successful.
vsim test.v
# vsim test.v
# ** Error: (vsim-19) Failed to access library 'test' at "test".
# No such file or directory. (errno = ENOENT)
# Error loading design



Can anyone using ModelSim Please help ?

Did you save your verilog or vhdl file under the working directory.
If not thn do it, hope it will solve the problem

 

[KellyB]

Did you save your verilog or vhdl file under the working directory.
If not thn do it, hope it will solve the problem

Thanks rickman and smqasim (I'm Sorry I don't know the names) for the
reply. I've managed to pin down the issue. Its working fine now.

Thanks Again