ModelSim newbie question (0/1)

[blf]

I am trying to complile the following code that is attached, from Ben
Cohen's book. Please look at VHD code.

I figure my problem is that I am not compiling a resource library
correctly. Can anybody give me step by step instructions on how to
make this work in ModelSim?

I have simulated a previous example of pre-written code and was able
to get a waveform generated, but it seems I don't know how to make
code to work if it has the following statement: johnson_1: entity
work_lib.johnson.

I know that it wants to see a lib called "work_lib" and I am assuming
that the code "johnson.vhd" should be located in it.

Below is the compiler error.

Thx


Compiler error message:

vcom -work work -93 -explicit {C:/Modeltech_xe/examples/projects/New
Folder/johnson_tb.vhd}
Model Technology ModelSim XE II vcom 5.7c Compiler 2003.03 Mar 15 2003
-- Loading package standard
-- Loading package std_logic_1164
-- Compiling entity johnson_tb
-- Compiling architecture johnsontop of johnson_tb
** Error: (vcom-11) Could not find work_lib.johnson.
** Error: C:/Modeltech_xe/examples/projects/New
Folder/johnson_tb.vhd(19): cannot find expanded name: work_lib.johnson
** Error: C:/Modeltech_xe/examples/projects/New
Folder/johnson_tb.vhd(19): Unknown field: johnson.
** Error: C:/Modeltech_xe/examples/projects/New
Folder/johnson_tb.vhd(27): VHDL Compiler exiting

 

[Jim Lewis]

Recommendation, use work rather than work_lib.
As a result,

Delete: library work_lib;
The library "work" is automatically referenced by VHDL.

Change: johnson_1: entity work_lib.johnson
To: johnson_1: entity work.johnson

Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:[email protected]
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

 

[Chrisitian Schneider]

Create the lib:
vlib work_lib

Compile the module to the lib:
vcom -work work_lib johnson.vhd
^^^^^^^^
this is the lib used by the tb


Chris

 

[ben cohen]

I used work_lib instead of "work" as my library. You need to create
the library and compile the mode into work_lib. Another option is to
modify the code so that all references to work_lib are changed to work
(you can do the search with a grep work_lib *.vhd.
Recommeded approach:
vlib work_lib
vcom -work work_lib -93 -explicit
c:/Modeltech_xe/examples/projects/NewFolder/johnson_tb.vhd

You probably don't need the explicit, unless the compiler complains.
Ben Cohen
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ (e-mail address removed)
Author of following textbooks:
* Using PSL/SUGAR with Verilog and VHDL
Guide to Property Specification Language for ABV, 2003 isbn
0-9705394-4-4
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn
0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn
0-7923-8115

 

[Jim Lewis]

"-explicit" flag is now the default in MTI.

Going beyond that, VHDL has a planned revision that
will always allow explicit declarations override
implicit declarations. Hopefully this issue will
be gone.

Cheers,
Jim
--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:[email protected]
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

 

[blf]

My Thanks to all. I am up and running with your help.