Modelsim post place and route/Post Translate issues

[Sridhar Hegde]

Hi,

Im new here so be gentle.My first post

I am trying to synthesize a ROM and it works out fine in Xilinx ISE
6.2.03i for Synthesize and Implement.However when I create a test
bench and try to see a Post Translate simulation result, I get
warnings about unbound components. Following is the warning and the
snippet of code that Im using.What am I doing wrong here....Any help
is appreciated!!!

I am getting the following warnings(a lot of them) when I synthesize
the following code for a ROM. What am I doing wrong?

On a post translate or a post place and route simulation, I get a 'U'
on my output pin...

The error I see looks something like
Warning: (vsim-3473) Component 'mmux_n0001_inst_mux_f8_3' is not
bound.
# Time: 0 ps Iteration: 0 Region: /inromtbw/uut File:
inrom_translate.vhd
# ** Warning: (vsim-3473) Component 'mmux_n0001_inst_mux_f5_49' is not
bound.
# Time: 0 ps Iteration: 0 Region: /inromtbw/uut File:
inrom_translate.vhd
# ** Warning: (vsim-3473) Component 'mmux_n0001_inst_mux_f5_32' is not
bound....

and so on

Code snippet for Inrom:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity inrom is
Port ( en : in std_logic;
clk : in std_logic;
dout : out std_logic_vector( 15 downto 0);--16 bit data that needs to
be input to the system
valid : out std_logic; --Tells that valid data is present on output
reset : in std_logic
);
end inrom;

architecture rtl of inrom is

type array_rom is array (31 downto 0) of std_logic_vector( 15 downto
0);
signal myarray : array_rom;
signal valid_sig:std_logic;
signal dout_sig : std_logic_vector(15 downto 0);
signal clk2: std_logic;

begin

myarray(0) <= x"0000";
myarray(1) <= x"0000";
myarray(2) <= x"0000";
myarray(3) <= x"003C";
myarray(4) <= x"0000";
myarray(5) <= x"0000";
myarray(6) <= x"0064";
myarray(7) <= x"0000";
myarray( <= x"0000";
myarray(9) <= x"000A";
myarray(10) <= x"0000";
myarray(11) <= x"0000";
myarray(12) <= x"003C";
myarray(13) <= x"0000";
myarray(14) <= x"0000";
myarray(15) <= x"0064";
myarray(16) <= x"0000";
myarray(17) <= x"0000";
myarray(18) <= x"0046";
myarray(19) <= x"0000";
myarray(20) <= x"0000";
myarray(21) <= x"006E";
myarray(22) <= x"0000";
myarray(23) <= x"0000";
myarray(24) <= x"000A";
myarray(25) <= x"0000";
myarray(26) <= x"0000";
myarray(27) <= x"0046";
myarray(28) <= x"0000";
myarray(29) <= x"0000";
myarray(30) <= x"006E";
myarray(31) <= x"0000";

process( reset,clk)
variable romvar:natural range 0 to 31;
--variable incr: boolean;

begin



if reset = '1' then
dout_sig <= (others=>'0');
valid_sig <='0';
romvar :=0;



elsif (clk'event and clk='1') then
if en='1' then

dout_sig <= myarray (romvar);
valid_sig<='1';
romvar :=romvar + 1;

else
dout_sig <= myarray (romvar);
valid_sig<='0';

end if;

end if;

end process;

dout <= dout_sig;
valid <=valid_sig;

end rtl;
===================================
Thanks in advance,
Sridhar

--------------------------------------------------------------------------------

 

[David Bishop]

Hi,

Im new here so be gentle.My first post

I am trying to synthesize a ROM and it works out fine in Xilinx ISE
6.2.03i for Synthesize and Implement.However when I create a test
bench and try to see a Post Translate simulation result, I get
warnings about unbound components. Following is the warning and the
snippet of code that Im using.What am I doing wrong here....Any help
is appreciated!!!

First, read the Synplicity style guide. They have a very specific
way that they want to see ROMs done. What you have will most likely
get crunched down to a boolean equation, and not a ROM.

Second you may consider building a ROM with the Xilinx CoreGen
tool. Then you can just plug it in.

I am getting the following warnings(a lot of them) when I synthesize
the following code for a ROM. What am I doing wrong?

Without seeing them, I can't say.

On a post translate or a post place and route simulation, I get a 'U'
on my output pin...

The error I see looks something like
Warning: (vsim-3473) Component 'mmux_n0001_inst_mux_f8_3' is not
bound.
# Time: 0 ps Iteration: 0 Region: /inromtbw/uut File:
inrom_translate.vhd
# ** Warning: (vsim-3473) Component 'mmux_n0001_inst_mux_f5_49' is not
bound.
# Time: 0 ps Iteration: 0 Region: /inromtbw/uut File:
inrom_translate.vhd
# ** Warning: (vsim-3473) Component 'mmux_n0001_inst_mux_f5_32' is not
bound....

and so on

Then a "U" is exactly what I would expect to see. It's not finding
this component.

Code snippet for Inrom:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;

Here is your first problem.
Either use "numeric_std" OR "std_logic_arith". Both define the types
"signed" and "unsigned". The rule in VHDL is that if two objects of
the same name are visible within a scope, then neither are visible.
You are not using the functionality in any of the last 3 packages.

-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity inrom is
Port ( en : in std_logic;
clk : in std_logic;
dout : out std_logic_vector( 15 downto 0);--16 bit data that needs to
be input to the system
valid : out std_logic; --Tells that valid data is present on output
reset : in std_logic
);
end inrom;

architecture rtl of inrom is

type array_rom is array (31 downto 0) of std_logic_vector( 15 downto
0);
signal myarray : array_rom;
signal valid_sig:std_logic;
signal dout_sig : std_logic_vector(15 downto 0);
signal clk2: std_logic;

begin

myarray(0) <= x"0000";
myarray(1) <= x"0000";
myarray(2) <= x"0000";
myarray(3) <= x"003C";
myarray(4) <= x"0000";
myarray(5) <= x"0000";
myarray(6) <= x"0064";
myarray(7) <= x"0000";
myarray( <= x"0000";
myarray(9) <= x"000A";
myarray(10) <= x"0000";
myarray(11) <= x"0000";
myarray(12) <= x"003C";
myarray(13) <= x"0000";
myarray(14) <= x"0000";
myarray(15) <= x"0064";
myarray(16) <= x"0000";
myarray(17) <= x"0000";
myarray(18) <= x"0046";
myarray(19) <= x"0000";
myarray(20) <= x"0000";
myarray(21) <= x"006E";
myarray(22) <= x"0000";
myarray(23) <= x"0000";
myarray(24) <= x"000A";
myarray(25) <= x"0000";
myarray(26) <= x"0000";
myarray(27) <= x"0046";
myarray(28) <= x"0000";
myarray(29) <= x"0000";
myarray(30) <= x"006E";
myarray(31) <= x"0000";

process( reset,clk)
variable romvar:natural range 0 to 31;
--variable incr: boolean;

begin



if reset = '1' then
dout_sig <= (others=>'0');
valid_sig <='0';
romvar :=0;



elsif (clk'event and clk='1') then
if en='1' then

dout_sig <= myarray (romvar);
valid_sig<='1';
romvar :=romvar + 1;

else
dout_sig <= myarray (romvar);
valid_sig<='0';

This looks functionally Ok. Must be something else going on.

 

[Ajeetha Kumari]

Hi,
Looks like during synthesis your tool has added the following
component

Component 'mmux_n0001_inst_mux_f8_3' is not
bound.
# Time: 0 ps Iteration: 0 Region: /inromtbw/uut File:
inrom_translate.vhd

For post synthesis simulation you will need to compile the VHDL src of
your target lib. In your file I see:

-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

So lib needs to be complied. What is your target lib anyway?

HTH,
Ajeetha


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