modelsim warnings

[srinukasam]

HI TO ALL
I designed a mux which gives multiple outputs. but at the time of
simulation with model sim iam getting some warning with generate command.
And my testbench is working for my design.the only problem is warning.i
want to get rid of those warnings.pls help me.

Warnings..

# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand,
the result will be 'X'(es).
# Time: 0 ns Iteration: 0 Instance: /mux_ge_tb/mut/ge1__5/mut1
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an
arithmetic operand, and it has been converted to 0.
# Time: 0 ns Iteration: 0 Instance: /mux_ge_tb/mut/ge1__5/mut1
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand,
the result will be 'X'(es).
# Time: 0 ns Iteration: 0 Instance: /mux_ge_tb/mut/ge1__4/mut1
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an
arithmetic operand, and it has been converted to 0.
# Time: 0 ns Iteration: 0 Instance: /mux_ge_tb/mut/ge1__4/mut1
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand,
the result will be 'X'(es).
# Time: 0 ns Iteration: 0 Instance: /mux_ge_tb/mut/ge1__3/mut1
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an
arithmetic operand, and it has been converted to 0.
# Time: 0 ns Iteration: 0 Instance: /mux_ge_tb/mut/ge1__3/mut1
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand,
the result will be 'X'(es).
# Time: 0 ns Iteration: 0 Instance: /mux_ge_tb/mut/ge1__2/mut1
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an
arithmetic operand, and it has been converted to 0.
# Time: 0 ns Iteration: 0 Instance: /mux_ge_tb/mut/ge1__2/mut1
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand,
the result will be 'X'(es).
# Time: 0 ns Iteration: 0 Instance: /mux_ge_tb/mut/ge1__1/mut1
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an
arithmetic operand, and it has been converted to 0.
# Time: 0 ns Iteration: 0 Instance: /mux_ge_tb/mut/ge1__1/mut1
# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand,
the result will be 'X'(es).
# Time: 0 ns Iteration: 0 Instance: /mux_ge_tb/mut/ge1__0/mut1
# ** Warning: CONV_INTEGER: There is an 'U'|'X'|'W'|'Z'|'-' in an
arithmetic operand, and it has been converted to 0.
# Time: 0 ns Iteration: 0 Instance: /mux_ge_tb/mut/ge1__0/mut1


DESIGN FOR COMPONENT-----

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity mux is
generic ( input_w :integer :=16; --input signal width
ictrl_w :integer :=4); -- individual control signal
width

port(input:in std_logic_vector (input_w-1 downto 0);
ctrl: in std_logic_vector (ictrl_w-1 downto 0);
out_muxut std_logic);
end entity mux;

architecture mux_beh of mux is
begin
out_mux<=input(conv_integer(ctrl));
end architecture mux_beh;

COMPONENT IS USED IN THIS DESIGN -------

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;


ENTITY mux_ge IS
generic ( input_w :integer :=16; --input signal width
ictrl_w :integer :=4; -- individual control signal
width
tctrl_w : integer :=24; -- total control signal width--mem
out
no_out,no_ctrl :integer :=6); -- no of output
signals(r),no.of control signals (V)

port( input:in std_logic_vector(input_w-1 downto 0);
tctrl: in std_logic_vector(tctrl_w-1 downto 0);
out_fmuxut std_logic_vector(no_out-1 downto 0));
END ENTITY mux_ge;

--
ARCHITECTURE mux_ge_str OF mux_ge IS

component mux

generic ( input_w :integer :=16; --input signal width
ictrl_w :integer :=4); -- individual control signal
width

port(input:in std_logic_vector(input_w-1 downto 0);
ctrl:in std_logic_vector(ictrl_w-1 downto 0);
out_mux: out std_logic);
end component mux;


BEGIN
ge1:for i in 0 to no_out-1 generate

mut1:mux port map(input,tctrl((i*ictrl_w)+(ictrl_w-1) downto
i*ictrl_w),out_fmux(i));
end generate ge1;


END ARCHITECTURE mux_ge_str;

configuration mux_ge_config of mux_ge is
for mux_ge_str
for all:mux
use entity work.mux(mux_beh);
end for;
end for;
end configuration mux_ge_config;

 

[Hubble]

The error lies in the conv_integer function,
which sees undefined values ("UUU..") at
simulation start. On some simulators,
the warnings can be disabled.

You could create a "wrapper" to conv_integer
and call this:

(not tested)

architecture ...

function my_conv_integer(s: std_logic_vector)
return integer is
begin
if s=(s'range => 'U') then -- avoid warning at start
return 0;
else
return conv_integer(s);
end if;
end my_conv_integer;

begin
....
out_mux<=my_conf_integer(ctrl);
....

 

[srinukasam]

hello
thank you very much for giving reply to my problem.
i tried with your solution( user defined function) ,eventough its giving
the same warnings..
here iam giving my test bench also..if you have time please try once (the
souce code i already sent in my first req.)
thank you


LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;


ENTITY mux_ge_stim IS

port( input : out std_logic_vector(15 downto 0);
tctrl : out std_logic_vector(23 downto 0);
out_fmux : in std_logic_vector(5 downto 0));


END ENTITY mux_ge_stim;

ARCHITECTURE mux_ge_stim_beh OF mux_ge_stim IS
BEGIN
stimuli: process
begin
input<="0000000000000000" after 0 ns,
"1111111111111111" after 14 ns,
"0000000011111111" after 24 ns,
"1111111100000000" after 34 ns,
"1111000011110000" after 44 ns,
"0000111100001111" after 54 ns;

tctrl<="000000010010001101000101" after 0 ns,
"011001111000100111001101" after 14 ns,
"000100110101011110011101" after 24 ns,
"000000100100011010001100" after 34 ns,
"111110101110100101110000" after 44 ns,
"000001010111100100111101" after 54 ns;



wait;
end process stimuli;

controlrocess
begin
--wait for 3 ns;
-- assert(mux_out="000000")report "z is false at 3 ns" severity
failure;
wait for 5 ns;
assert(out_fmux="000000")report "out_fmux is false at 5 ns" severity
failure;
wait for 10 ns;
assert(out_fmux="111111")report "out_fmux is false at 15 ns" severity
failure;
wait for 10 ns;
assert(out_fmux="111100")report "out_fmux is false at 25 ns" severity
failure;
wait for 10 ns;
assert(out_fmux="000011")report "out_fmux is false at 35 ns" severity
failure;
wait for 10 ns;
assert(out_fmux="101010")report "out_fmux is false at 45 ns" severity
failure;
wait for 10 ns;
assert(out_fmux="100110")report "out_fmux is false at 55 ns" severity
failure;

wait;
end process control;
end mux_ge_stim_beh;
----
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;


ENTITY mux_ge_tb IS
END ENTITY mux_ge_tb;

--
ARCHITECTURE mux_ge_tb_stru OF mux_ge_tb IS

component mux_ge_stim
port(
input : out std_logic_vector(15 downto 0);
tctrl : out std_logic_vector(23 downto 0);
out_fmux : in std_logic_vector(5 downto 0));

end component;
component mux_ge
port(
input : in std_logic_vector(15 downto 0);
tctrl : in std_logic_vector(23 downto 0);
out_fmux : out std_logic_vector(5 downto 0));

end component;


signal input:std_logic_vector(15 downto 0);
signal tctrl:std_logic_vector(23 downto 0);
signal out_fmux:std_logic_vector(5 downto 0);

BEGIN
stimuli : mux_ge_stim port map(input,tctrl,out_fmux);
mut: mux_ge port map(input,tctrl,out_fmux);
END mux_ge_tb_stru;

configuration mux_ge_tb_config of mux_ge_tb is
for mux_ge_tb_stru
for stimuli:mux_ge_stim
use entity work.mux_ge_stim(mux_ge_stim_beh);
end for;
for mut: mux_ge
use entity work.mux_ge(mux_ge_str);
end for;
end for;
end mux_ge_tb_config;

 

[Ralf Hildebrandt]

srinukasam wrote:

I designed a mux which gives multiple outputs. but at the time of
simulation with model sim iam getting some warning with generate command.
And my testbench is working for my design.the only problem is warning.i
want to get rid of those warnings.pls help me.

Warnings..

# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand,
the result will be 'X'(es).

Do you read my answers or do I post into a black hole?

If possible: Don't try to convert any signal of a type, that may be 'U',
'X', 'W', 'Z' or '-' (e.g. std_(u)logic_(vector), signed, unsiged) to
integer, because the integer data type cannot carry such values. Convert
the integer to the more complex type instead.

Another option may be to convert any signal, that is to be converted to
integer first to bit_vector. Because the type bit is eigther '1' or '0',
it can be converted to integer everytime. Conversion to bit_vector does
not output such warnings.


And again - yes - AGAIN! Shall I repeat it? *AGAIN*!
Do /not/ use

USE ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

but take

use ieee.numeric_std.all;

instead, because the first two libraries are not standard libraries.

Ralf

 

[Hans]

You can avoid the 'U'|'X'|'W'|'Z'|'-' warnings at time zero by replacing
your "run xx" by:

set StdArithNoWarnings 1
run 0 ns;
set StdArithNoWarnings 0
run xx;

Hans
www.ht-lab.com

 

[srinukasam]

hello Hans
i didnt understood what is your replacement for my problem( modelsim
error).
could you please send me some detailed reply.
thank you
bye

 

[Andy Peters]

hello Hans
i didnt understood what is your replacement for my problem( modelsim
error).
could you please send me some detailed reply.
thank you
bye

Sheesh.

Type the commands that Hans gave you into the ModelSim shell.

-a