module instantiation

P

pat

what am i trying to do...
i have a top module and a child module (see below code).
i am trying to have the child module return (via output) a counter number
that changes in sequence to the parent module.

what i have done...
i have tied the ouput [7:0] to 8 different LEDs and using the counter and
delay in parent module, LEDs count in binary. trying my child module, only
bit 0 is toggled on/off

what is happen'...
the child module is not counting to the depth of the output [7:0]. it is
returning only 1 or 0 (toggles the LSB LED on and off only)

here is the parent...
module top(clk, Out, Enable);

input clk;
output [7:0] Out;
input Enable;
reg [22:0] delay;
reg [7:0] test;
wire tapA0;

always @(posedge clk)
begin
if (Enable == 1)
begin
if (delay == 10)
test <= test + 1;
delay <= delay + 1;
end
else
test <= 0;
end

bottom first_lfsr (.clk(clk), .Enable(Enable), .delayA0(tapA0));

assign Out = tapA0;
endmodule

here is the child...

module bottom (clk, Enable, delayA0);

input clk;
input Enable;

output [7:0] delayA0;
reg [20:0] delay2;
reg [7:0] test2;

always @(posedge clk)
begin
if (Enable == 1)
begin
if (delay2 == 10)
test2 <= test2 + 1;
delay2 <= delay2 + 1;
end
else
test2 <= 0;
end
assign delayA0 = test2;

endmodule

HOW DO I get the child to return the full resolution and not just the LSB as
1 or 0.

Thanks in advance
Patrick
 
A

ALuPin

pat said:
what am i trying to do...
i have a top module and a child module (see below code).
i am trying to have the child module return (via output) a counter number
that changes in sequence to the parent module.

what i have done...
i have tied the ouput [7:0] to 8 different LEDs and using the counter and
delay in parent module, LEDs count in binary. trying my child module, only
bit 0 is toggled on/off

what is happen'...
the child module is not counting to the depth of the output [7:0]. it is
returning only 1 or 0 (toggles the LSB LED on and off only)

here is the parent...
module top(clk, Out, Enable);

input clk;
output [7:0] Out;
input Enable;
reg [22:0] delay;
reg [7:0] test;
wire tapA0;

always @(posedge clk)
begin
if (Enable == 1)
begin
if (delay == 10)
test <= test + 1;
delay <= delay + 1;
end
else
test <= 0;
end

bottom first_lfsr (.clk(clk), .Enable(Enable), .delayA0(tapA0));

assign Out = tapA0;
endmodule

here is the child...

module bottom (clk, Enable, delayA0);

input clk;
input Enable;

output [7:0] delayA0;
reg [20:0] delay2;
reg [7:0] test2;

always @(posedge clk)
begin
if (Enable == 1)
begin
if (delay2 == 10)
test2 <= test2 + 1;
delay2 <= delay2 + 1;
end
else
test2 <= 0;
end
assign delayA0 = test2;

endmodule

HOW DO I get the child to return the full resolution and not just the LSB as
1 or 0.

Thanks in advance
Patrick

VHDL?
 

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