R
RishiD
Hi,
Making a FSM in VHDL. Problem is my tlCount and pauseCount has two
drivers, one in state_reg process and one in the next_state_logic
process. I cannot seem a good way to fix this but still keep them
seperated, I don't want to combine the state_reg process and
next_state_logic process into one. Need to keep the code clean.
Thanks for the help,
Rishi
state_reg:
process (clk, reset) begin
if (reset = '1') then
CURRENT_STATE <= Zero;
tlCount <= 0;
pauseCount <= 0;
elsif (clk'event and clk = '1') then
CURRENT_STATE <= NEXT_STATE;
tlCount <= tlCount + 1;
pauseCount <= pauseCount + 1;
end if;
end process;
next_state_logic:
process (CURRENT_STATE, NSsensor, EWsensor) begin
case CURRENT_STATE is
when Zero => NEXT_STATE <= NSg;
when NSg =>
if (tlCount >= 30 and EWsensor) then
NEXT_STATE <= NSpause;
pauseCount <= 0;
elsif (tlCount = 60) then
NEXT_STATE <= NSy;
tlCount <= 0;
else
NEXT_STATE <= NSg;
end if;
............
end case;
end process;
output_logic:
process (CURRENT_STATE) begin .....
Making a FSM in VHDL. Problem is my tlCount and pauseCount has two
drivers, one in state_reg process and one in the next_state_logic
process. I cannot seem a good way to fix this but still keep them
seperated, I don't want to combine the state_reg process and
next_state_logic process into one. Need to keep the code clean.
Thanks for the help,
Rishi
state_reg:
process (clk, reset) begin
if (reset = '1') then
CURRENT_STATE <= Zero;
tlCount <= 0;
pauseCount <= 0;
elsif (clk'event and clk = '1') then
CURRENT_STATE <= NEXT_STATE;
tlCount <= tlCount + 1;
pauseCount <= pauseCount + 1;
end if;
end process;
next_state_logic:
process (CURRENT_STATE, NSsensor, EWsensor) begin
case CURRENT_STATE is
when Zero => NEXT_STATE <= NSg;
when NSg =>
if (tlCount >= 30 and EWsensor) then
NEXT_STATE <= NSpause;
pauseCount <= 0;
elsif (tlCount = 60) then
NEXT_STATE <= NSy;
tlCount <= 0;
else
NEXT_STATE <= NSg;
end if;
............
end case;
end process;
output_logic:
process (CURRENT_STATE) begin .....