multisourcing problem

[deep]

I am new to vhdl development . I am trying to model a I2C bus master and
slave, making components of each.the signal SDA and SCL are being fed in
both components i.e. master and slave.I am facing two problems:
1] when I call components in the design , there is a problem of multi
sourcing on "SDA" signal, when I write SDA in both components.I have
declared it as an inout port .

2] when I donot write in both cases i.e. write to"SDA" only in one of
components, but keep SDA as "inout" in both the components, it does not
changes the value of SDA.

I am synthesising in Xilinx and simulating in Modelsim .

Could anyone help me ...the code is described below...

Deep






entity I2C is
port ( rst : in std_logic;
clk: in std_logic;
sda : inout std_logic;
scl : inout std_logic;
data_in : in std_logic_vector( 7 downto 0) ;
data_out : out std_logic_vector( 7 downto 0)
);
end I2C;

architecture I2C_a of I2C is
type wrrd is ( wr, rd);
signal mode1: wrrd;
signal mode: std_logic;
signal data : std_logic_vector(7 downto 0);

component i2c_master is
port (rst : in std_logic;
clk: in std_logic;
sdam : inout std_logic;
sclm : out std_logic;
mode : inout std_logic;
data : in std_logic_vector( 7 downto 0)
);
end component;

component i2c_slave is
port (rst : in std_logic;
clk: in std_logic;
sdas : inout std_logic;
scls : in std_logic;
mode : in std_logic;
data : out std_logic_vector( 7 downto 0)
);
end component;



begin

port map(rst => rst,clk => clk,sdam=> sda,sclm=> scl,mode=>
mode,data=> data_in);

port map (rst=> rst, clk=> clk,sdas=>sda, scls=>scl, mode=> mode,
data=> data_out);

end I2C_a;

 

[deep]

I missed the details of the components:

master: I2C_master port map(rst => rst,clk => clk,sdam=> sda,sclm=>
scl,mode=>
mode,data=> data_in);

Slave: I2C_slave port map (rst=> rst, clk=> clk,sdas=>sda,
scls=>scl, mode=> mode,
data=> data_out);

--deep

 

[Anders Hellerup Madsen]

I am new to vhdl development . I am trying to model a I2C bus master and
slave, making components of each.the signal SDA and SCL are being fed in
both components i.e. master and slave.I am facing two problems:
1] when I call components in the design , there is a problem of multi
sourcing on "SDA" signal, when I write SDA in both components.I have
declared it as an inout port .

2] when I donot write in both cases i.e. write to"SDA" only in one of
components, but keep SDA as "inout" in both the components, it does not
changes the value of SDA.

I am synthesising in Xilinx and simulating in Modelsim .

Could anyone help me ...the code is described below...

Deep

Inout ports have to be assigned Z's when you aren't writing to them.
Otherwise you won't be able to read anything put into them from the
other side:


inout_port <= write_data when (write_enable = '1') else (others => '0');
read_data <= inout_port;

 

[Anders Hellerup Madsen]

inout_port <= write_data when (write_enable = '1') else (others => '0');

Or for ¤@¤%"!'s sake, the above line should have been:

inout_port <= write_data when (write_enable = '1') else (others => 'Z');

Note the 'Z' in the end.

 

[deep]

SDAM/SDAS has either to be written or read in both entities, so I cannot
keep it in Z state. SO I feel multi-source problem would occur. I donot
want to make more interfaces in two entities.could there be a better way
to write code.

following is the problem faced:

WARNING:Xst:528 - Multi-source in Unit <i2c> on signal <N599> not replaced
by logic
Signal is stuck at GND
ERROR:Xst:415 - Synthesis failed

Deep

 

[Ray Andraka]

If I understand your question properly, you have a bidirectional line which
can be driven by multiple sources. I assume this is at a point outside of
your chip...eg at the board level design. If inside the chip, you'll want to
keep the recievers and transmitters separate and use gates to combine them
into a common receive and a common transmit, and then bring those out to the
periphery with a tristate driver on the transmit. The common recieve inside
the chip would be the logical OR of the internal transmits and the receive
from the chip periphery. For simulation, you may have to model a pull-up
resistor for the external tristate line to get proper simulation.

SDAM/SDAS has either to be written or read in both entities, so I cannot
keep it in Z state. SO I feel multi-source problem would occur. I donot
want to make more interfaces in two entities.could there be a better way
to write code.

following is the problem faced:

WARNING:Xst:528 - Multi-source in Unit <i2c> on signal <N599> not replaced
by logic
Signal is stuck at GND
ERROR:Xst:415 - Synthesis failed

Deep

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email (e-mail address removed)
http://www.andraka.com

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