A
Andrew FPGA
Hi,
In the past I have sucessfully used the following style to infer a
multiplexor.
variable : mux_input : std_logic_vector(3 downto 0);
variable : mux_output : std_logic;
variable : mux_select : natural range 0 to 3;
.....
mux_output := mux_input(mux_select);
It seems a lot more elegant than the seemingly industry standard
if/else or case style.
However, when I try to select over a non power of 2 range,( i.e. in the
above example, mux_input would be non power of 2 ) XST gives me the
following ominous warning:
WARNING:Xst:790 - "C:/projec.....vhd" line 282: Index value(s) does not
match array range, simulation mismatch.
1) Does anyone use/like the above mux style?
2) Does anyone know how to use this style to select over ranges that
are non power of 2?
(Just to be clear - I'm talking about for synthesis here..)
Regards
Andrew
In the past I have sucessfully used the following style to infer a
multiplexor.
variable : mux_input : std_logic_vector(3 downto 0);
variable : mux_output : std_logic;
variable : mux_select : natural range 0 to 3;
.....
mux_output := mux_input(mux_select);
It seems a lot more elegant than the seemingly industry standard
if/else or case style.
However, when I try to select over a non power of 2 range,( i.e. in the
above example, mux_input would be non power of 2 ) XST gives me the
following ominous warning:
WARNING:Xst:790 - "C:/projec.....vhd" line 282: Index value(s) does not
match array range, simulation mismatch.
1) Does anyone use/like the above mux style?
2) Does anyone know how to use this style to select over ranges that
are non power of 2?
(Just to be clear - I'm talking about for synthesis here..)
Regards
Andrew