need correction 16 bit risc processor code

S

selva991

hello guys can i get complte code for a 16 bit risc processor written
in VHDL, i have developed code for it but im not sure whether it is
correct can any one correct my code


-HEADER FILE INTILISATION
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

--ALU INPUT DECLARATION

entity pro is
port(a,b:in std_logic_vector(7 downto 0);
s: in std_logic_vector(3 downto 0);
y: out std_logic_vector(9 downto 0)
);
end pro;

--ALU ARCHITECHURE MODULE

architecture project of pro is
signal temp:std_logic_vector(9 downto 0);
begin
process(a,b,s)
begin
--ACCORDING TO CONTROL SIGNAL
--ARTHMATIC OR LOGICAL FUNCTION SELECTION
case s is
when "0000"
=> temp<=a+b;
when "0001"
=> temp<=a-b;
when "0010"
=> temp<=a*b;
when "0100"
=> temp<=a and b;
when "0101"
=> temp<=a or b;
when others
=>temp<=a xor b;

end case ;

end process;
--PRINT OUTPUT
y<=temp;
end project;


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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;



entity CPU is
port (
PADDR : out std_logic_vector(31 downto 0);
PDATA : in std_logic_vector(15 downto 0);
O_PRAM_DOUT : out std_logic_vector(15 downto 0);
PORTA_IN : in std_logic_vector(7 downto 0);
PORTA_OUT : out std_logic_vector(7 downto 0);
PORTA_OE_L : out std_logic_vector(7 downto 0);

PORTB_IN : in std_logic_vector(7 downto 0);
PORTB_OUT : out std_logic_vector(7 downto 0);
PORTB_OE_L : out std_logic_vector(7 downto 0);

PORTC_IN : in std_logic_vector(7 downto 0);
PORTC_OUT : out std_logic_vector(7 downto 0);
PORTC_OE_L : out std_logic_vector(7 downto 0);

PORTD_IN : in std_logic_vector(7 downto 0);
PORTD_OUT : out std_logic_vector(7 downto 0);
PORTD_OE_L : out std_logic_vector(7 downto 0);

DEBUG_W : out std_logic_vector(7 downto 0);
DEBUG_PC : out std_logic_vector(10 downto 0);
DEBUG_INST : out std_logic_vector(15 downto 0);
DEBUG_STATUS : out std_logic_vector(7 downto 0);

RESET : in std_logic;
CLK : in std_logic
);
end;

architecture RTL of CPU is

-- component definitions

component IDEC is
port (
INST : in std_logic_vector(11 downto 0);

ALU_ASEL : out std_logic_vector(1 downto 0);
ALU_BSEL : out std_logic_vector(1 downto 0);
ALU_ADDSUB : out std_logic_vector(1 downto 0);
ALU_BIT : out std_logic_vector(1 downto 0);
ALU_SEL : out std_logic_vector(1 downto 0);

WWE_OP : out std_logic;
FWE_OP : out std_logic;

ZWE : out std_logic;
DCWE : out std_logic;
CWE : out std_logic;
BDPOL : out std_logic;
OPTION : out std_logic;
TRIS : out std_logic
);
end component;

component ALU is
port (
ADDSUB : in std_logic_vector(1 downto 0);
BIT : in std_logic_vector(1 downto 0);
SEL : in std_logic_vector(1 downto 0);

A : in std_logic_vector(7 downto 0);
B : in std_logic_vector(7 downto 0);
Y : out std_logic_vector(7 downto 0);
CIN : in std_logic;
COUT : out std_logic;
DCOUT : out std_logic;
ZOUT : out std_logic
);
end component;

component REGS is
port (
WE : in std_logic;
RE : in std_logic;
BANK : in std_logic_vector(1 downto 0);
LOCATION : in std_logic_vector(4 downto 0);
DIN : in std_logic_vector(7 downto 0);
DOUT : out std_logic_vector(7 downto 0);
RESET : in std_logic;
CLK : in std_logic
);
end component;

-- type/constant definitions
constant STATUS_RESET_VALUE : std_logic_vector(7 downto 0) := x"18";
constant OPTION_RESET_VALUE : std_logic_vector(7 downto 0) := x"3F";
constant INDF_ADDR : std_logic_vector(2 downto 0) := "000";
constant TMR0_ADDR : std_logic_vector(2 downto 0) := "001";
constant PCL_ADDR : std_logic_vector(2 downto 0) := "010";
constant STATUS_ADDR : std_logic_vector(2 downto 0) := "011";
constant FSR_ADDR : std_logic_vector(2 downto 0) := "100";
constant PORTA_ADDR : std_logic_vector(2 downto 0) := "101";
constant PORTB_ADDR : std_logic_vector(2 downto 0) := "110";
constant PORTC_ADDR : std_logic_vector(2 downto 0) := "111";
constant PORTD_ADDR : std_logic_vector(2 downto 0) := "111";

-- signal definitions
signal inst : std_logic_vector(15 downto
0);

signal inst_k : std_logic_vector(7 downto 0);
signal inst_fsel : std_logic_vector(4 downto 0);
signal inst_d : std_logic;
signal inst_b : std_logic_vector(2 downto 0);
signal tmr0 : std_logic_vector(1 downto 0);
signal pc,next_pc : std_logic_vector(31 downto
0);
signal pc_load_stack : std_logic_vector(10 downto
0);
signal pc_write : std_logic_vector(10 downto
0);

signal stacklevel : std_logic_vector(1 downto 0);
signal stack1,stack2 : std_logic_vector(10 downto
0);

signal porta_dout : std_logic_vector(7 downto 0);
signal portb_dout : std_logic_vector(7 downto 0);
signal portc_dout : std_logic_vector(7 downto 0);
signal portd_dout : std_logic_vector(7 downto 0);

signal porta_din : std_logic_vector(7 downto 0);
signal portb_din : std_logic_vector(7 downto 0);
signal portc_din : std_logic_vector(7 downto 0);
signal portd_din : std_logic_vector(7 downto 0);

signal dbus,sbus : std_logic_vector(7 downto 0);
signal sbus_swap : std_logic_vector(7 downto 0);
signal sbus_mux_out : std_logic_vector(7 downto 0);

-- inst decode
signal regfile_sel,special_sel : std_logic;
signal fileaddr_indirect : std_logic;
signal fileaddr_mux1 : std_logic_vector(6 downto 0);
signal fileaddr_mux0 : std_logic_vector(6 downto 0);

signal istris,isoption : std_logic;
signal fwe,wwe,zwe,dcwe,cwe : std_logic;
signal bdpol,status1 : std_logic;
signal bd,trisa,trisb,trisc,trisd :
std_logic_vector(7 downto 0);
signal skip : std_logic;

-- alu
signal alu_asel,alu_bsel : std_logic_vector(1 downto 0)
;
signal alu_addsub : std_logic_vector(1 downto 0)
;
signal alu_bit : std_logic_vector(1 downto 0)
;
signal alu_sel : std_logic_vector(1 downto 0)
;

signal alu_z,alu_dcout,alu_cout : std_logic ;
signal alu_a,alu_b : std_logic_vector(7 downto 0)
;
signal alu_out : std_logic_vector(7 downto 0);

signal regfile_we,regfile_re : std_logic;
signal regfile_in,regfile_out : std_logic_vector(7 downto 0);
signal fileaddr : std_logic_vector(6 downto 0);

begin -- architecture


u_regs : REGS
port map (
WE => regfile_we,
RE => regfile_re,
BANK => fileaddr(6 downto 5),
LOCATION => fileaddr(4 downto 0),
DIN => regfile_in,
DOUT => regfile_out,
RESET => RESET,
CLK => CLK
);

DEBUG_PC <= pc(10 downto 0);
DEBUG_INST <= inst;

-- *********** REGISTER FILE Addressing ****************

p_regfile_we_comb : process(regfile_sel,fwe,alu_asel,alu_bsel)
begin
regfile_we <= regfile_sel and fwe;
regfile_re <= '1'; -- not used
end process;

p_fileaddr_dec_comb : process(fileaddr,isoption,istris)
begin
regfile_sel <= '1'; -- everything else;
special_sel <= '0';
if (fileaddr(4 downto 3) = "00") and (isoption = '0') and (istris =

'0') then
special_sel <= '1'; -- lower 8 addresses in ALL BANKS 1 lut
end if;
end process;


p_dbus_comb : process(alu_out)
begin
dbus <= alu_out;
regfile_in <= alu_out;
end process;

p_paddr_comb : process(next_pc)
begin
PADDR <= next_pc(31 downto 0);
end process;

p_inst_assign_comb : process(inst)
begin
inst_k <= inst(7 downto 0);
inst_fsel <= inst(4 downto 0);
inst_d <= inst(5);
inst_b <= inst(7 downto 5);
end process;

p_bdec_assign_comb : process(inst_b,bdpol)
variable bdec : std_logic_vector(7 downto 0);
begin
-- 1 lut
bdec := "00000001";
case inst_b is
when "000" => bdec := "00000001";
when "001" => bdec := "00000010";
when "010" => bdec := "00000100";
when "011" => bdec := "00001000";
when "100" => bdec := "00010000";
when "101" => bdec := "00100000";
when "110" => bdec := "01000000";
when "111" => bdec := "10000000";
when others => null;
end case;
if (bdpol = '1') then
bd <= not bdec;
else
bd <= bdec;
end if;
end process;

p_inst : process(CLK,RESET)
begin
if (RESET = '1') then
inst <= "0000000000000000";
elsif CLK'event and (CLK = '1') then
if (skip = '1') then
inst <= "0000000000000000"; -- force NOP
else
inst <= PDATA;
end if;
end if;
end process;

p_skip_comb : process(inst,alu_z,fwe,special_sel,fileaddr)
begin
-- SKIP signal.
-- We want to insert the NOP instruction for the following
conditions:
-- we have modified PCL
-- GOTO,CALL and RETLW instructions
-- BTFSS instruction when aluz is HI
-- BTFSC instruction when aluz is LO
skip <= '0';

if (fwe = '1') and (special_sel = '1') and (fileaddr(2 downto 0) =
PCL_ADDR) then skip <= '1'; end if;
if (inst(11 downto 10) = "10") then skip <= '1'; end if;
if (inst(11 downto 8) = "0110") and (alu_z = '1') then skip <=
'1'; end if; -- BTFSC
if (inst(11 downto 8) = "0111") and (alu_z = '0') then skip <=
'1'; end if; -- BTFSS
if (inst(11 downto 6) = "001011") and (alu_z = '1') then skip <=
'1'; end if; -- DECFSZ
if (inst(11 downto 6) = "001111") and (alu_z = '1') then skip <=
'1'; end if; -- INCFSZ
end process;

sbus_swap <= sbus(3 downto 0) & sbus(7 downto 4);


port_in : process(CLK,RESET,PORTA_IN,PORTB_IN,PORTC_IN)
begin
-- the input registers don't exist in the real device,
-- so if you read an output we have introduced a clock delay.
if (RESET = '1') then
porta_din <= (others => '0');
portb_din <= (others => '0');
portc_din <= (others => '0');
portd_din <= (others => '0');
elsif CLK'event and (CLK = '1') then -- comment this out for
combinatorial ip
porta_din <= PORTA_IN;
portb_din <= PORTB_IN;
portc_din <= PORTC_IN;
portd_din <= PORTD_IN;
end if;
end process;

p_port_reg : process(CLK,RESET)
begin
if (RESET = '1') then
trisa <= "11111111"; -- default tristate
trisb <= "11111111"; -- default tristate
trisc <= "11111111"; -- default tristate
trisd <= "11111111"; -- default tristate
porta_dout <= x"00";
portb_dout <= x"00";
portc_dout <= x"00";
portd_dout <= x"00";
elsif CLK'event and (CLK = '1') then

if (fwe = '1') and (fileaddr(2 downto 0) = PORTA_ADDR) then
if (istris = '0') and (special_sel = '1') then
porta_dout <= dbus;
elsif (istris = '1') then
trisa <= dbus;
end if;
end if;

if (fwe = '1') and (fileaddr(2 downto 0) = PORTB_ADDR) then
if (istris = '0') and (special_sel = '1') then
portb_dout <= dbus;
elsif (istris = '1') then
trisb <= dbus;
end if;
end if;

if (fwe = '1') and (fileaddr(2 downto 0) = PORTC_ADDR) then
if (istris = '0') and (special_sel = '1') then
portc_dout <= dbus;
elsif (istris = '1') then
trisc <= dbus;
end if;
end if;
if (fwe = '1') and (fileaddr(2 downto 0) = PORTD_ADDR) then
if (istris = '0') and (special_sel = '1') then
portd_dout <= dbus;
elsif (istris = '1') then
trisd <= dbus;
end if;
end if;

end if;
end process;

-- ********** PC AND STACK *************************



p_stack_comb : process(stacklevel,stack1,stack2)
begin
pc_load_stack <= stack1; -- default
case stacklevel is
when "00" => pc_load_stack <= stack1;
when "01" => pc_load_stack <= stack1;
when "10" => pc_load_stack <= stack2;
when "11" => pc_load_stack <= stack2;
when others => null;
end case;
end process;

p_stack_reg : process(CLK,RESET)
begin
if (RESET = '1') then
stack1 <= (others => '0');
stack2 <= (others => '0');
elsif CLK'event and (CLK = '1') then
if (inst(11 downto 8) = "1001") then
case stacklevel is
when "00" => stack1 <= pc(10 downto 0);
when "01" => stack2 <= pc(10 downto 0);
when others => null;
end case;
end if;
end if;
end process;

p_stack_level : process(CLK,RESET)
begin
if (RESET = '1') then
stacklevel <= "00";
elsif CLK'event and (CLK = '1') then
stacklevel <= stacklevel;
if (inst(11 downto 8) = "1001") then
case stacklevel is
when "00" => stacklevel <="01"; -- 1st call
when "01" => stacklevel <="10"; -- 2nd call
when "10" => stacklevel <="10"; -- already 2, ignore
when "11" => stacklevel <="00"; -- broke
when others => null;
end case;
elsif (inst(11 downto 8) = "1000") then
case stacklevel is
when "00" => stacklevel <="00"; -- broke
when "01" => stacklevel <="00"; -- go back to no call
when "10" => stacklevel <="01"; -- go back to 1 call
when "11" => stacklevel <="10"; -- broke
when others => null;
end case;
end if;
end if;
end process;
end rtl;
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library IEEE;
use IEEE.std_logic_1164.all;

entity keyboard is
port (
Key_0: in STD_LOGIC;
Key_1: in STD_LOGIC;
Key_2: in STD_LOGIC;
Key_3: in STD_LOGIC;
Key_4: in STD_LOGIC;
Key_5: in STD_LOGIC;
Key_6: in STD_LOGIC;
Key_7: in STD_LOGIC;
Key_8: in STD_LOGIC;
Key_9: in STD_LOGIC;
RESET: in STD_LOGIC;
ACKA: in STD_LOGIC;
INTA: out STD_LOGIC;
CODE: out STD_LOGIC_VECTOR (3 downto 0)
);
end keyboard;

--}} End of automatically maintained section

architecture keyboard of keyboard is
signal INT: std_logic;
begin
-- <<enter your statements here>>
process(Key_0,Key_1,Key_2,Key_3,Key_4,Key_5,Key_6,Key_7,Key_8,Key_9,Key_0,

ACKA, RESET)
begin
if(RESET='1') then
INT<='1';
CODE<="0000";
else
if(INT='1' and (ACKA='1' or ACKA='H')) then
if(Key_0='1') then
CODE<="0000";
INT<='0';
elsif(Key_1='1') then
CODE<="0001";
INT<='0';
elsif(Key_2='1') then
CODE<="0010";
INT<='0';
elsif(Key_3='1') then
CODE<="0011";
INT<='0';
elsif(Key_4='1') then
CODE<="0100";
INT<='0';
elsif(Key_5='1') then
CODE<="0101";
INT<='0';
elsif(Key_6='1') then
CODE<="0110";
INT<='0';
elsif(Key_7='1') then
CODE<="0111";
INT<='0';
elsif(Key_8='1') then
CODE<="1000";
INT<='0';
elsif(Key_9='1') then
CODE<="1001";
INT<='0';
else
INT<='1';
end if;
elsif(INT='0' and ACKA='0') then
INT<='1';
end if;
end if;
end process;

INTA<=INT;
end keyboard;
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.pkg_xilinx_prims.all;

entity RISC5X_XIL is
port (
I_PRAM_ADDR : in std_logic_vector(31 downto 0);
I_PRAM_DIN : in std_logic_vector(15 downto 0);
O_PRAM_DOUT : out std_logic_vector(15 downto 0);
I_PRAM_WE : in std_logic;
I_PRAM_ENA : in std_logic;
PRAM_CLK : in std_logic;
--
IO_PORTA_IO : inout std_logic_vector(7 downto 0);
IO_PORTB_IO : inout std_logic_vector(7 downto 0);
IO_PORTC_IO : inout std_logic_vector(7 downto 0);
IO_PORTD_IO : inout std_logic_vector(7 downto 0);

O_DEBUG_W : out std_logic_vector(7 downto 0);
O_DEBUG_PC : out std_logic_vector(10 downto 0);
O_DEBUG_INST : out std_logic_vector(11 downto 0);
O_DEBUG_STATUS : out std_logic_vector(7 downto 0);

RESET : in std_logic;
CLK : in std_logic
);
end;

architecture RTL of RISC5X_XIL is
signal porta_in : std_logic_vector(7 downto 0);
signal porta_out : std_logic_vector(7 downto 0);
signal porta_oe_l : std_logic_vector(7 downto 0);

signal portb_in : std_logic_vector(7 downto 0);
signal portb_out : std_logic_vector(7 downto 0);
signal portb_oe_l : std_logic_vector(7 downto 0);

signal portc_in : std_logic_vector(7 downto 0);
signal portc_out : std_logic_vector(7 downto 0);
signal portc_oe_l : std_logic_vector(7 downto 0);

signal portd_in : std_logic_vector(7 downto 0);
signal portd_out : std_logic_vector(7 downto 0);
signal portd_oe_l : std_logic_vector(7 downto 0);

signal paddr : std_logic_vector(31 downto 0);
signal pdata,pin : std_logic_vector(15 downto 0);
signal pram_addr : std_logic_vector(10 downto 0);
signal pram_din : std_logic_vector(11 downto 0);
signal pram_dout : std_logic_vector(11 downto 0);
signal pram_we : std_logic;
signal pram_ena : std_logic;

signal debug_w : std_logic_vector(7 downto 0);
signal debug_pc : std_logic_vector(10 downto 0);
signal debug_inst : std_logic_vector(15 downto 0);
signal debug_status : std_logic_vector(7 downto 0);

signal doa_temp : std_logic_vector(11 downto 0);
signal dob_temp : std_logic_vector(11 downto 0);

component CPU is
port (
PADDR : out std_logic_vector(31 downto 0);
PDATA : in std_logic_vector(15 downto 0);
O_PRAM_DOUT : out std_logic_vector(15 downto 0);
PORTA_IN : in std_logic_vector(7 downto 0);
PORTA_OUT : out std_logic_vector(7 downto 0);
PORTA_OE_L : out std_logic_vector(7 downto 0);

PORTB_IN : in std_logic_vector(7 downto 0);
PORTB_OUT : out std_logic_vector(7 downto 0);
PORTB_OE_L : out std_logic_vector(7 downto 0);

PORTC_IN : in std_logic_vector(7 downto 0);
PORTC_OUT : out std_logic_vector(7 downto 0);
PORTC_OE_L : out std_logic_vector(7 downto 0);

PORTD_IN : in std_logic_vector(7 downto 0);
PORTD_OUT : out std_logic_vector(7 downto 0);
PORTD_OE_L : out std_logic_vector(7 downto 0);

DEBUG_W : out std_logic_vector(7 downto 0);
DEBUG_PC : out std_logic_vector(10 downto 0);
DEBUG_INST : out std_logic_vector(15 downto 0);
DEBUG_STATUS : out std_logic_vector(7 downto 0);
-- out_DATA : out std_logic_vector(15 downto 0);
RESET : in std_logic;
CLK : in std_logic
);
end component;

begin
u0 : CPU
port map (
PADDR => paddr,
PDATA => pdata,
O_PRAM_DOUT => pin,
PORTA_IN => porta_in,
PORTA_OUT => porta_out,
PORTA_OE_L => porta_oe_l,

PORTB_IN => portb_in,
PORTB_OUT => portb_out,
PORTB_OE_L => portb_oe_l,

PORTC_IN => portc_in,
PORTC_OUT => portc_out,
PORTC_OE_L => portc_oe_l,

PORTD_IN => portd_in,
PORTD_OUT => portd_out,
PORTD_OE_L => portd_oe_l,

-- DEBUG_W => debug_w,
-- DEBUG_PC => debug_pc,
-- DEBUG_INST => debug_inst,
-- DEBUG_STATUS => debug_status,

RESET => RESET,
CLK => CLK
);

p_drive_ports_out_comb :
process(porta_out,porta_oe_l,portb_out,portb_oe_l,portc_out,portc_oe_l)
begin
pin<= I_PRAM_DIN;
for i in 0 to 7 loop
if (porta_oe_l(i) = '0') then
IO_PORTA_IO(i) <= porta_out(i);
else
IO_PORTA_IO(i) <= 'Z';
end if;

if (portb_oe_l(i) = '0') then
IO_PORTB_IO(i) <= portb_out(i);
else
IO_PORTB_IO(i) <= 'Z';
end if;

if (portc_oe_l(i) = '0') then
IO_PORTC_IO(i) <= portc_out(i);
else
IO_PORTC_IO(i) <= 'Z';
end if;
if (portd_oe_l(i) = '0') then
IO_PORTD_IO(i) <= portd_out(i);
else
IO_PORTD_IO(i) <= 'Z';
end if;
end loop;
end process;

p_drive_ports_in_comb : process(IO_PORTA_IO,IO_PORTB_IO,IO_PORTC_IO)
begin
O_PRAM_DOUT <= pin;
porta_in <= IO_PORTA_IO;
portb_in <= IO_PORTB_IO;
portc_in <= IO_PORTC_IO;
portd_in <= IO_PORTC_IO;
end process;
end RTL;
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--HEADER FILE INTILI SATION
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.pkg_xilinx_prims.all;


--There are three memory blocks in each of the risc devices.
--The program memory and data
--memory have separate buses so that concurrent
---access can occur and is detailed in this section. The
--EEPROM data memory block is detailed in
--"Data EEPROM and Flash Program Memory".
--Additional information on device memory may be found

--The data memory is partitioned into multiple banks
--which contain the General Purpose Registers and the
--Special Function Registers. Bits RP1 (Status<6>) and
--R-P0 (Status<5>) are the bank select bits.
--REGISTER INPUT OUTPUT DECLARATION
entity REGS is
port (
WE : in std_logic;
RE : in std_logic;
BANK : in std_logic_vector(1 downto 0);
LOCATION : in std_logic_vector(4 downto 0);
DIN : in std_logic_vector(7 downto 0);
DOUT : out std_logic_vector(7 downto 0);
RESET : in std_logic;
CLK : in std_logic
);
end;
--

architecture RTL of REGS is

constant WIDTH : natural := 8;
constant OP_REG : boolean := false;

type slv_array is array (natural range <>) of
std_logic_vector(WIDTH-1 downto 0);
signal ram_out : slv_array(4 downto 0);
signal wen_int : std_logic_vector(4 downto 0);
signal sel : std_logic_vector(2 downto 0);
signal final_addr : std_logic_vector(6 downto 0);
--constant WIDTH : natural := 8;
--constant OP_REG : boolean := false;

-- following required for simulation model only
constant nwords : integer := 2 ** 7;
type ram_type is array (0 to nwords-1) of std_logic_vector(WIDTH-1
downto 0);
signal ram_read_data : std_logic_vector(WIDTH-1 downto 0);
--shared variable ram :ram_type := (others => (others => 'X')); --
helps debug no end!
shared variable ram :ram_type := (others => (others => '0'));

begin -- architecture

-- ram mapping
-- bank location
-- xx 00xxx special registers
-- xx 01xxx common 8 to all banks
-- 00 1xxxx 16 bank 0
-- 01 1xxxx 16 bank 1
-- 10 1xxxx 16 bank 2
-- 11 1xxxx 16 bank 3
DOUT<= DIN;
p_wen_comb : process (BANK,LOCATION,WE)
variable addr : std_logic_vector(3 downto 0);
begin
addr := (BANK & LOCATION(4 downto 3));
wen_int <= (others => '0');
case addr(3 downto 1) is
when "001" => wen_int(0) <= WE; -- bank0
when "011" => wen_int(1) <= WE; -- bank1
when "101" => wen_int(2) <= WE; -- bank2
when "111" => wen_int(3) <= WE; -- bank3

when others => null;
end case;
if (LOCATION(4 downto 3) = "01") then
wen_int(4) <= WE; -- common
end if;


SEL <= BANK & LOCATION(4);

end process;

--pragma translate_off


--The PIC16F87XA devices have a 13-bit program
--counter capable of addressing an 8K word x 14 bit
--program memory space. The risc
--devices have 8K words x 14 bits of Flash program
--memory,

p_remap : process(BANK,LOCATION)
variable addr : std_logic_vector(3 downto 0);
begin
addr := (BANK & LOCATION(4 downto 3));
final_addr <= "0000000";
case addr is
when "0001" => final_addr <= "0000" & LOCATION(2 downto 0);
when "0101" => final_addr <= "0000" & LOCATION(2 downto 0);
when "1001" => final_addr <= "0000" & LOCATION(2 downto 0);
when "1101" => final_addr <= "0000" & LOCATION(2 downto 0);
-- bank #0
when "0010" => final_addr <= "0001" & LOCATION(2 downto 0);
when "0011" => final_addr <= "0010" & LOCATION(2 downto 0);
-- bank #1
when "0110" => final_addr <= "0011" & LOCATION(2 downto 0);
when "0111" => final_addr <= "0100" & LOCATION(2 downto 0);
--bank #2
when "1010" => final_addr <= "0101" & LOCATION(2 downto 0);
when "1011" => final_addr <= "0110" & LOCATION(2 downto 0);
-- bank #3
when "1110" => final_addr <= "0111" & LOCATION(2 downto 0);
when "1111" => final_addr <= "1000" & LOCATION(2 downto 0);
when others => null;
end case;
end process;
end RTL;
 
M

Mike Treseler

hello guys can i get complte code for a 16 bit risc processor written
in VHDL, i have developed code for it but im not sure whether it is correct
can any one correct my code
Click to expand...

Yes, you can.
Write a testbench and run a simulation.
Edit code, repeat.

-- Mike Treseler
 
M

Mark McDougall

Mark McDougall wrote:

Actually, I think it's pretty obvious this guy didn't even write the
code in question.

Why steal code you don't know works?

Regards,
 
U

Uncle Noah

Mark said:
Actually, I think it's pretty obvious this guy didn't even write the
code in question.
Why steal code you don't know works?
Click to expand...

Agree with you. It looks like this code is taken from some other
student (alumni in his institution?) He probably can't get in touch
with him/her, and want us to get his job done.

Uncle Noah
 

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