W
Weng Tianxiang
Hi,
1. Based on the previous very benefitial discussions and my
observation on the topics, I decide to recant the following claim:
Whatever assertion onehot0() can do, 'orif' can do better.
2. In place of the above claim, I claim the following new one:
Whatever assertion onehot() can do, it can do better working together
with new keyword 'OIF'.
3. Rolin has indicated that orif has been used in 2006 version.
4. The following simplest example show why point 2 is justified. The
more equations, the more complicated added statements distributed over
the full entity to transfer the information to VHDL compiler.
METHOD 1:
if(TWindowLoad_E0_L_H and nC_BE_R0(3) = '0') then
TWindow_3(10 downto 8) <= AD_R0(26 downto 24);
OIF(TWindowLoad_E0_H_H and nC_BE_R0(7) = '0') then
TWindow_3(10 downto 8) <= AD_R0(58 downto 56);
end if;
METHOD 2: current VHDL-2006.
signal B2 : unsigned(1 downto 0);
B2(0) <= '1' when TWindowLoad_E0_L_H and nC_BE_R0(3) = '0' else '0';
B2(1) <= '1' when TWindowLoad_E0_H_H and nC_BE_R0(7) = '0' else '0';
assertion onehot0(B2);
if(B2(0) = '1') then
TWindow_3(10 downto 8) <= AD_R0(26 downto 24);
orif(B2(1) = '1') then
TWindow_3(10 downto 8) <= AD_R0(58 downto 56);
end if;
5. Thank you everone who paticipates on the topics.
Weng
1. Based on the previous very benefitial discussions and my
observation on the topics, I decide to recant the following claim:
Whatever assertion onehot0() can do, 'orif' can do better.
2. In place of the above claim, I claim the following new one:
Whatever assertion onehot() can do, it can do better working together
with new keyword 'OIF'.
3. Rolin has indicated that orif has been used in 2006 version.
4. The following simplest example show why point 2 is justified. The
more equations, the more complicated added statements distributed over
the full entity to transfer the information to VHDL compiler.
METHOD 1:
if(TWindowLoad_E0_L_H and nC_BE_R0(3) = '0') then
TWindow_3(10 downto 8) <= AD_R0(26 downto 24);
OIF(TWindowLoad_E0_H_H and nC_BE_R0(7) = '0') then
TWindow_3(10 downto 8) <= AD_R0(58 downto 56);
end if;
METHOD 2: current VHDL-2006.
signal B2 : unsigned(1 downto 0);
B2(0) <= '1' when TWindowLoad_E0_L_H and nC_BE_R0(3) = '0' else '0';
B2(1) <= '1' when TWindowLoad_E0_H_H and nC_BE_R0(7) = '0' else '0';
assertion onehot0(B2);
if(B2(0) = '1') then
TWindow_3(10 downto 8) <= AD_R0(26 downto 24);
orif(B2(1) = '1') then
TWindow_3(10 downto 8) <= AD_R0(58 downto 56);
end if;
5. Thank you everone who paticipates on the topics.
Weng