Newbee in VHDL

[Ruud]

Hallo allemaal,


I think I'm new here. If not, then it was quite some years back, when
I was fiddling with CPLDs. But that didn't get off the ground; I
preferred the real 74-stuff above the CPLDs (it is just hobby for me,
not my profession).
But lately I was pointed to the Godil, < http://www.oho-elektronik.de/

, a module with a big FPGA plus some extras that can replace (IMHO)

any 40/48 pins DIL-IC. Some guys already used it in a BBC Master to
replace the onboard 65C102, <
http://sites.google.com/site/beeb816/project-updates/firstbytefromthetube-on-fpgahimemis32768

.

I bought the header version because I already had several ideas for
its use and and almost none included direct IC replacement. One of the
ideas is replacing the 6510 of my Commodore 64 with an, as compatible
as possible, improved CPU.

I have been busy with building my own 6502, < http://www.baltissen.org/newhtm/ttl6502.htm

, and I decided to use an updated, not yet published design as base

for my own VHDL design. Yes, I know, there are some free 6502 VHDL
designs around. I studied T65, available at OpenCores. The T65 core is
used in many reliable working designs < http://www.fpgaarcade.com/library.htm

.

I understood (mostly of) its parts but not the whole. And this has to
do with the concepts of concurrency, sequential and event-driven. I
program in Pascal and Delphy and therefore are familiar with
sequential and event-driven code. You can say that, by working with
TTL-ICs, I'm familiar concurrency, but also with things like delay and
glitches.

I'll give you an example where things go wrong in my vision. According
the docs the RDY signal stops the 6502 when pulled low and there is no
write going on. RDY is checked at the end of the upper part of the
clock. Here is an excerpt from the T65 code:


architecture rtl of T65 is
signal really_rdy : std_logic;
...
begin
really_rdy <= Rdy or not(R_W_n_i); [1]
R_W_n <= R_W_n_i;
....

process (Clk) [2]
begin
if Clk'event and Clk = '1' then [3]
if (Enable = '1') then
if (really_rdy = '1') then [4]
.....
IRQ_n_o <= IRQ_n;
NMI_n_o <= NMI_n;
end if;
end if;
end if;
end process;


I interprete it as that the signal really_rdy at [1] is updated _all_
the time. The process [2] is only handled if Clk has changed. I
interprete [3] as: "handle the following lines if Clk has become '1'".
And I interprete [4] as: "and do it only if RDY is not active". I can
imagine that RDY has been activated moments before CLK became '1' but
also that this situation can change half-way the upper Clk cycle, well
before the cycle of Clk. Inthat case the 6502 is stopped while it
shouldn't.

IRQ is level triggered. IMHO now it it checked at the beginning of the
upper part of Clk while IMHO it should be at the end.
NMI is edge triggered and should have its own process IMHO.

To make sure my TTL6502 is 6502 compatible, it must use both phases of
Clk. AFAIK T65 only uses the phase Clk = '1', as in above example.
IMHO this could only be done because a big FPGA enables you to execute
some tasks parallel, tasks I have to do sequential because I only have
an 8 bits wide internal data bus.


Of course I have been programming myself already and want to show you
the base so you can shoot at it:

begin
IRQ_in <= not(IRQ) when (PHI0 = '1');
RDY_in <= not(RDY) when ((PHI0 = '1') and (PHI_in = '1')); [1]

process(NMI) [2]
begin
if (RESET = '0') then
NMI_in <= '1'; -- set internal NMI flag
end if;
end process;

process(RESET, PHI0)
begin
if (RESET = '0') then
.....
NMI_in <= '0'; -- reset internal NMI flag
elsif PHI0'event then
if (RDY_in = '1') then [3]
if (PHI0 = '0') then
PHI_in <= '0';
.....
else
PHI_in <= '1';
....
end if;
end if;
end if;
end process;
end;

[1]: RDY_in can be set only during the upper half of PHI0 and only
after the event of the process has been executed;
[2] makes sure that NMI is edge triggered.
[3] this RDY_in can only have been set in previous upper half of PHI0
IMHO.


Two questions:
- please comment my above thoughts.
- just popped up: how can I test my design as best as possible? FYI: i
have an ISA card with 96 I/O lines connected to my Godil. So I can use
Turbo Pascal under DOS to address every in- or outpu of the Godil. Any
hint is welcome!

Many thanks in advance !!!


Kind regards, Ruud Baltissen

www.Baltissen.org

 

[jeppe]

Hi Ruud

My standard answer for VHDL newbees always - try to search the free book "Evita VHDL" - it will learn some essential stuff about how VHDL "works"

the use of rising_edge( clk) and falling_edge( clk) could solve some of your problems - but the "final solution" could be a statemachine which gives you full control over the actual timing of signals.

More about state machines here: jjmk.dk/MMMI/Statemachines/Pages1/statemachines.htm

Your welcome
Jeppe