newbie question

[Florian Student]

Dear Comp.lang.vhdl,

I've been trying to write a simple free running 8 bit counter. Here's
the source I got so far:

// Module Declaration
module counter
(
clk, out
);
// Port Declaration
input clk;
output [7:0] out;
reg [7:0] counter;

always @(posedge clk)
begin
counter = counter + 1;
out = counter;
end

endmodule

The Quartus compiler tells me that there's an
"Error: Verilog HDL Procedural Assignment error at counter.v(21):
illegal Procedural Assignment to nonregister data type out"

What am I doing wrong?

Thanx in advance,

Florian

 

[paris]

Dear Comp.lang.vhdl,

I've been trying to write a simple free running 8 bit counter. Here's
the source I got so far:

// Module Declaration
module counter
(
clk, out
);
// Port Declaration
input clk;
output [7:0] out;
reg [7:0] counter;

always @(posedge clk)
begin
counter = counter + 1;
out = counter;
end

endmodule

The Quartus compiler tells me that there's an
"Error: Verilog HDL Procedural Assignment error at counter.v(21):
illegal Procedural Assignment to nonregister data type out"

What am I doing wrong?

Thanx in advance,

Florian

well, like you said, this is comp.lang.VHDL and your code is in Verilog
if you dont get the answers here you could try comp.lang.verilog
just in case, Verilog and VHDL (VHSIC HDL) are different HDLs

 

[Dave Townsend]

I believe you need to declare the output port as a register. It is
not legal in verilog to assign in a always block to a wire ( plain old
port).

dave

Dear Comp.lang.vhdl,

I've been trying to write a simple free running 8 bit counter. Here's
the source I got so far:

// Module Declaration
module counter
(
clk, out
);
// Port Declaration
input clk;
output [7:0] out;
reg [7:0] counter;

always @(posedge clk)
begin
counter = counter + 1;
out = counter;
end

endmodule

The Quartus compiler tells me that there's an
"Error: Verilog HDL Procedural Assignment error at counter.v(21):
illegal Procedural Assignment to nonregister data type out"

What am I doing wrong?

Thanx in advance,

Florian

well, like you said, this is comp.lang.VHDL and your code is in Verilog
if you dont get the answers here you could try comp.lang.verilog
just in case, Verilog and VHDL (VHSIC HDL) are different HDLs