V
valentin tihomirov
I have some questions regarding Xilinx design flow.
What NGD and NGC files are? Is edif file created by the 2edif tools
synthesizable?
According to
http://toolbox.xilinx.com/docsan/xilinx4/data/docs/dev/ngdbuild2.html,
NGDBuild converts netlist (Edif, Ngc, Xnf) into logical design (ngd - logic
elements like AND gates, decoders, FFs, RAMs). This is called translation.
But what is a role of synthezier, isn't it XST that should generate netlist
of logic gates from RTL description? ActiveHDL IDE allows for functional,
post-synthess and timing (post-implementation) simulations. Sinthesis is
done using Sinplify; it includes two stages: compilation and mapping. After
syntesis, Xilinx implementation tools are used to get timing information.
Implementation consists of translation, mapping (again?) and P&R. Why
mapping is done twice?
Why two different libraries (Unisim and SimPrim) are used for syntesis and
implementation? Wouldn't it be more effective to use only one? Can I write a
structural edif file based on elements of those libraries (which one?) and
synthetize it effectively creating design from scratch bypassing synthesis?
Thanks.
What NGD and NGC files are? Is edif file created by the 2edif tools
synthesizable?
According to
http://toolbox.xilinx.com/docsan/xilinx4/data/docs/dev/ngdbuild2.html,
NGDBuild converts netlist (Edif, Ngc, Xnf) into logical design (ngd - logic
elements like AND gates, decoders, FFs, RAMs). This is called translation.
But what is a role of synthezier, isn't it XST that should generate netlist
of logic gates from RTL description? ActiveHDL IDE allows for functional,
post-synthess and timing (post-implementation) simulations. Sinthesis is
done using Sinplify; it includes two stages: compilation and mapping. After
syntesis, Xilinx implementation tools are used to get timing information.
Implementation consists of translation, mapping (again?) and P&R. Why
mapping is done twice?
Why two different libraries (Unisim and SimPrim) are used for syntesis and
implementation? Wouldn't it be more effective to use only one? Can I write a
structural edif file based on elements of those libraries (which one?) and
synthetize it effectively creating design from scratch bypassing synthesis?
Thanks.