M
moogyd
Hi,
(Off-topic, Cross-posted to comp.lang.vhdl and comp.lang.verilog)
I am looking to put an open-source bug/issue tracking system in place
for our current project (eventually expanded for all projects), and
would appreciate any experiences/comments/suggestions.
I am also going to solicit suggestions on a couple of S/W groups, but I
really need comments from a ASIC/ASSP design flow perspective.
The easiest method is using a spreadsheet, but this is not very
expandable.
The requirements I have come up with
- Free ;-)
- Easy to setup and maintain (I want this to be an engieering tool, not
an IT project)
- A non linux expert should be able to download and install (rpms OK,
deep understanding of makefiles and linux kernel not OK)
- Ideally via text files, a bit of perl/tcl/etc OK. I'd rather avoid
SQL
- Prove the system and then hand-off to IT for maintenance
- Easy use
- Browser UI
- Mail ?
- Linux
- Flexible reporting/search
- User/admin accounts
- Initially internal network access only, eventually external
(customer, partner) access
- Cover HDL, H/W, F/W, Documentation, Change requests. Both ASIC and
FPGA.
- Eventually production issues (Yeild, Test programs?)
- Maybe allow project deadlines included.
- We use CVS, so any loose coupling useful
- We have per project repositories, plus and repository containing
common IP's (i.e a project will always use 2)
- Medium size projects (upto 15-20 people
- Possible migration to other system in future (which I guess means a
well supported database)
Googling provided with lots of names
- Bugzilla (seems to be in widest use for S/W projects)
- GNATS (I recall using this in a previous job)
- IssueTrackerSystem (ZOPE, Python)
- Trac (Python)
- Plus lots of others
Any suggestions, comments, recommendations or pointers to
papers/tutorals greatly appreciated.
Steven
(Off-topic, Cross-posted to comp.lang.vhdl and comp.lang.verilog)
I am looking to put an open-source bug/issue tracking system in place
for our current project (eventually expanded for all projects), and
would appreciate any experiences/comments/suggestions.
I am also going to solicit suggestions on a couple of S/W groups, but I
really need comments from a ASIC/ASSP design flow perspective.
The easiest method is using a spreadsheet, but this is not very
expandable.
The requirements I have come up with
- Free ;-)
- Easy to setup and maintain (I want this to be an engieering tool, not
an IT project)
- A non linux expert should be able to download and install (rpms OK,
deep understanding of makefiles and linux kernel not OK)
- Ideally via text files, a bit of perl/tcl/etc OK. I'd rather avoid
SQL
- Prove the system and then hand-off to IT for maintenance
- Easy use
- Browser UI
- Mail ?
- Linux
- Flexible reporting/search
- User/admin accounts
- Initially internal network access only, eventually external
(customer, partner) access
- Cover HDL, H/W, F/W, Documentation, Change requests. Both ASIC and
FPGA.
- Eventually production issues (Yeild, Test programs?)
- Maybe allow project deadlines included.
- We use CVS, so any loose coupling useful
- We have per project repositories, plus and repository containing
common IP's (i.e a project will always use 2)
- Medium size projects (upto 15-20 people
- Possible migration to other system in future (which I guess means a
well supported database)
Googling provided with lots of names
- Bugzilla (seems to be in widest use for S/W projects)
- GNATS (I recall using this in a previous job)
- IssueTrackerSystem (ZOPE, Python)
- Trac (Python)
- Plus lots of others
Any suggestions, comments, recommendations or pointers to
papers/tutorals greatly appreciated.
Steven