Parameterisable number of shift reg components

[scs9gp]

Hi everyone.

i want to make a design with a number of shift registers. The number of shift registers is controlled by a parameter 'b'.

how can i do that?

For now i try the folloing but is not working:

GEN: FOR i IN 1 TO b GENERATE
a1: ENTITY sftreg GENERIC MAP(width=>8) PORT MAP(clk,sin(i),pout(i));
END GENERATE GEN;

Each register is 8-bit width
'clk' is std_logic type
'sin' is a std_logic_vector(1 TO b) type
'pout' is a array2D type defined as bellow

TYPE array2D IS ARRAY (b DOWNTO 1) OF std_logic_vector(width DOWNTO 1);

It seems to me (maybe i am wrong) that vhdl does not support parameterisable number of instance statements in a generate because of the instance statementy label.

Thank you
George