Parse error

[Kausi]

I want to convert a function into a component. When i originally use
the function the code works correctly without errors. But when i use a
component instead of the function, it results in Parse error.
Can anyone explain why?

Regards,
Kauser.

 

[Tricky]

I want to convert a function into a component. When i originally use
the function the code works correctly without errors. But when i use a
component instead of the function, it results in Parse error.
Can anyone explain why?

Regards,
Kauser.

Not unless you post the code.

 

[Kausi]

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


----------------Entity
description---------------------------------------
entity integer_squareroot is
port(D: inout bit_vector(7 downto 0);
Q: inout bit_vector(3 downto 0);
Remainder: out bit_vector(4 downto 0);
CLK: in bit);
end integer_squareroot;
---------------Main
Architecture-----------------------------------------

architecture Behavioral of integer_squareroot is
---------------Function-
addsub-----------------------------------------
function addsub( a,b : bit_vector(3 downto 0);
c : bit;
ctrl : bit) return bit_vector is
variable sum: bit_vector(4 downto 0);
variable temp: bit;
begin
temp:=c;
if (ctrl='1') then
for i in 0 to 3 loop
sum(i) := a(i) xor b(i) xor temp;
temp:= (a(i) and b(i)) or (b(i) and temp) or (temp and a(i));
end loop;
sum(4):=temp;
else
if(temp='0') then
temp:= not temp;
for i in 0 to 3 loop
sum(i) := a(i) xor b(i) xor temp;
temp := ((not a(i)) and b(i)) or (b(i) and temp) or (temp and (not
a(i)));
end loop;
sum(4):=temp;
else
temp:= not temp;
for i in 0 to 3 loop
sum(i) := a(i) xor b(i) xor temp;
temp := ((not a(i)) and b(i)) or (b(i) and temp) or (temp and (not
a(i)));
end loop;
sum(4):=temp;
end if;
end if;
return sum;
end addsub;
---------------end function-
addsub-----------------------------------------

type dstate is range 3 downto 0;
signal state : dstate :=3;

begin
---------------The process state begins
here----------------------------
process(state)
variable r0: bit_vector(1 downto 0);
variable r2: bit_vector(4 downto 0);
variable c_temp,control: bit:='0';
variable A,B: bit_vector(3 downto 0):="0000";
variable r : bit_vector(3 downto 0);
variable sh : bit_vector(3 downto 0);
begin
case state is
when 3 =>
c_temp:=D(7) or D(6);
r0(0):= not D(6);
r0(1):= D(7) xnor D(6);
B:=sh;
A:=sh;
control:=r2(3);
r2:=addsub(A,B,c_temp,control);
sh:=sh(2 downto 0)& (not r2(3));
r:=r2(1 downto 0)& r0(1 downto 0);
Q<=sh;
when 2 =>
c_temp:=D(5) or D(4);
r0(0):= not D(4);
r0(1):= D(5) xnor D(4);
B:=sh;
A:=r;
control:=r2(3);
r2:=addsub(A,B,c_temp,control);
sh:=sh(2 downto 0)& (not r2(3));
r:=r2(1 downto 0)& r0(1 downto 0);
Q<=sh;
when 1 =>
c_temp:=D(3) or D(2);
r0(0):= not D(2);
r0(1):= D(3) xnor D(2);
B:=sh;
A:=r;
control:=r2(3);
r2:=addsub(A,B,c_temp,control);
sh:=sh(2 downto 0)& (not r2(3));
r:=r2(1 downto 0)& r0(1 downto 0);
Q<=sh;
when 0 =>
c_temp:=D(1) or D(0);
r0(0):= not D(0);
r0(1):= D(1) xnor D(0);
B:=sh;
A:=r;
control:=r2(3);
r2:=addsub(A,B,c_temp,control);
sh:=sh(2 downto 0)& (not r2(3));
r:=r2(1 downto 0)& r0(1 downto 0);
end case;

Q<=sh;
Remainder(4 downto 0)<= (r2(2 downto 0) & r0(1 downto 0));
end process;
--------------------------------------------------------
process(CLK)
begin
if(CLK='1' and CLK'event and state/=0) then
state<=state-1;
end if;
end process;
----------------------------------------------------------

end Behavioral;


Note the function addsub in the above program. When i convert it into
a component and call it in the main program it returns a parse error.

r2:=addsub(A,B,c_temp,control); -- This is where iam calling the
function addsub now. I tried a component at the same location.

 

[Kausi]

To, Jonathan Bromley

 

[kennheinrich]

To, Jonathan Bromley
-------------------------------------------------------------------
What do you mean, "at the same location"? It makes no sense> to put a component (either a declaration, or an instance) in

------------------------------------------------------------------

I tried that already. But it still returns the parse error. Could it
be because iam calling the component inside a process statement? Is it
allowed?

No, it is not allowed. Instantiating a component is considered a
"parallel" statement, because the component can go off and do other
things on its own. A function call to compute a value is considered a
"sequential" statement because it happens in-line with the other code
statements you're executing. Inside a process you can only write
sequential statements. Inside the top level of an architecture you
always write parallel statements. A good book on VHDL (or some more
googling for VHDL syntax) should fill in the rest.

If you want to put the function "into a component" so that it's easy
to share and re-use, you're on the wrong track. Take the advice above
and put it into a package. On the other hand, if you want to put it
into a component so that you have a component, you'll only be able to
use it in the appropriate context.

- Kenn

 

[kennheinrich]

No, it is not allowed. Instantiating a component is considered a
"parallel" statement, because the component can go off and do other

Clarification... in VHDL terminology this is called a concurrent
statement, not a parallel statement. If you're searching the web, use
this term.

- Kenn

 

[Kausi]

Thank you for your valuable advice. I have done precisely that. Have
included the function inside a package and using it now. One more
thing, if i write another program and call the above one as a
component, should i be able to proceed? As since the one above doesnt
entirely use concurrent statements. Iam a beginner and hope these
aren't the kind of questions considered nonsensical.

Regards,
Kauser.

 

[kennheinrich]

Thank you for your valuable advice. I have done precisely that. Have
included the function inside a package and using it now. One more
thing, if i write another program and call the above one as a
component, should i be able to proceed? As since the one above doesnt
entirely use concurrent statements. Iam a beginner and hope these
aren't the kind of questions considered nonsensical.

Regards,
Kauser.

The code you originally posted contains what is called in VHDL an
"entity", which defines nothing more than the I/O of a black box that
you might want to instantiate at some point, along with an
"architecture", which tells a synthesizer or a simulator how to build
or model the black box. So as long as you realize that there are only
certain places where you are allowed to instantiate a component (never
inside a process or inside a function or subprogram body, for
example), then yes, you can re-use the entity/architecture code you
wrote.

Incidentally, the (or at least my) preferred way to instantiate the
"component" (which in this case is an entity) is *not* to write a
separate component declaration, the way many on-line examples are
written. This is archaic and is just extra work. There's usually no
need for a separate component declaration, just use the entity
directly. Instead, in the architecture of your higher level module,
just include the square root entity directly like so:


architecture example of something_bigger
....
begin
sqrt_1 : entity work.integer_squareroot port map (clk => top_clk, d=>
top_d, q => top_q, remainder => top_rem);
....
end architecture example;

to hook up to your top level signals. You can instantiate a pair of
these and build a module which computes x^(1/4) for example.

- Kenn

 

[Kausi]

It was simply awesome.. Haven't encountered that method in any of the
normally followed guides. It sure makes sense to do that. Thanks Kenn.