partial aggregate assignment?

[jens]

Hi,

I'm trying to do a partial aggregate assigment, this fragmented
pseudo-code shows what I'm trying to do... (INDEX1 and INDEX2 are
constants between 0 and 31)

signal test_vector: std_logic_vector(31 downto 0);

test_vector <= (INDEX1 => open, INDEX2 => open, others => '1');

process1...
test_vector(INDEX1) <= {logic};
end process;

process2...
test_vector(INDEX2) <= {logic};
end process;

I'm trying to assign most of the vector to '1' and have two separate
processes assign the remaining two bits. The compiler doesn't like
"open" or "null", and any other assignment wouldn't resolve correctly
('-' resolves to 'X', 'U' resolves to 'U', I'm trying to avoid 'Z'
because the code should work with any FPGA). On the other hand, maybe
'Z' is the answer and the FPGA compiler will be smart enough to not
implement a tri-state signal in an architecture that doesn't support
internal tri-states. I'm currently using an Altera Stratix FPGA but it
needs to be portable to any other vendor.

Another option is to combine the two processes into one and use a
default assignment for the whole vector, but I'm trying to avoid
changing more than I need to (I inherited the design). I suppose
another option is to use a loop and only assign certain elements, or
use three assigment statements like:

test_vector(INDEX1-1 downto 0) <= (others => '1');
test_vector(INDEX2-1 downto INDEX1+1) <= (others => '1');
test_vector(31 downto INDEX2+1) <= (others => '1');

But that makes some assumptions about the values of INDEX1 and INDEX2
and can get kind of convoluted, especially if INDEX3 needs to be added
later.

It seems like there should be an easier and more elegant way.

Thanks in advance for any advice...

 

[Mike Treseler]

I'm trying to assign most of the vector to '1' and have two separate
processes assign the remaining two bits.

Your choices are combine the processes or split the signal.

I'm trying to avoid
changing more than I need to (I inherited the design).

It's yours now.


-- Mike Treseler