Passing a signal from slow to fast clock

[Divyang M]

Hi,
I've looked over the discussion in the forum on passing signal between
clock domains and read Clifford Cummings paper on asynchronous clock
design and coded a synchronizer circuit.

The problem is the I have a pulse coming in from a slow clock and this
has to be sampled by the fast clk which could lead to the signal being
active for more than 1 clk cycle in the fast clk.
So I've added edge detection in the synchronizer circuit. I think this
should do the trick. Can I get some expert opinion if this is correct
since it seems there is no way to thoroughly test a sync circuit
(easily).

port(
pCLK : in std_logic;
NEWLINE_v : in std_logic;
NEWLINE_p : out std_logic
);
end sync_v2p;

architecture RTL of sync_v2p is
signal stage1fifo,
stage2fifo,
pulsefifo : std_logic;

begin
process(pCLK) is
begin
if (pCLK = '1' and pCLK'event) then

-- perform two stage synchronization
-- as in SNUG2001 paper by Clifford Cummings
stage1fifo <= NEWLINE_v;
stage2fifo <= stage2fifo;

-- add third stage for edge detection
pulsefifo <= stage2fifo;

-- detect edge and assign output
if (stage2fifo = '1' and pulsefifo = '0') then
NEWLINE_p <= '1';
else
NEWLINE_p <= '0';
end if;

end if;
end process;
end RTL;

Also if I don't do edge detection in the sync circuit but use the
following piece of code in my block will it work and synthesize? (just
curious)

if (pCLK = '1 and pCLK'event) then
-- assume synchronizer is only 2 stage
-- and no edge detection is done in synchronizer
-- detect edge here
if (NEWLINE_p = '1' and NEWLINE_P'event) then

...

end if;

I have never seen 'event being used anywhere except for the clk which
is why I am asking this.

Thanks,
Divyang M

 

[Divyang M]

Just a correction above in a typo..
it should be

stage1fifo <= NEWLINE_v;
stage2fifo <= stage1fifo;

 

[Neo]

divyang,
You are just checking for the rising edge of the data but not the
duration. so your output will always be one clock cycle in faster
domain even if the data remains high for multiple clock cycles in the
slower domain. This modification should check for that:
if ((stage2fifo = '1' and pulsefifo = '0') or stage1fifo = '1') then

 

[Jim Lewis]

Divyang,Use 'event only with clocks. They imply connection
to the clock input of a flip-flop.

Better yet if all your clock signals are std_logic, use
the rising_edge function:

if rising_edge(Clk) then

Cheers,
Jim

I've looked over the discussion in the forum on passing signal between
clock domains and read Clifford Cummings paper on asynchronous clock
design and coded a synchronizer circuit.

The problem is the I have a pulse coming in from a slow clock and this
has to be sampled by the fast clk which could lead to the signal being
active for more than 1 clk cycle in the fast clk.
So I've added edge detection in the synchronizer circuit. I think this
should do the trick. Can I get some expert opinion if this is correct
since it seems there is no way to thoroughly test a sync circuit
(easily).

port(
pCLK : in std_logic;
NEWLINE_v : in std_logic;
NEWLINE_p : out std_logic
);
end sync_v2p;

architecture RTL of sync_v2p is
signal stage1fifo,
stage2fifo,
pulsefifo : std_logic;

begin
process(pCLK) is
begin
if (pCLK = '1' and pCLK'event) then

-- perform two stage synchronization
-- as in SNUG2001 paper by Clifford Cummings
stage1fifo <= NEWLINE_v;
stage2fifo <= stage2fifo;

-- add third stage for edge detection
pulsefifo <= stage2fifo;

-- detect edge and assign output
if (stage2fifo = '1' and pulsefifo = '0') then
NEWLINE_p <= '1';
else
NEWLINE_p <= '0';
end if;

end if;
end process;
end RTL;

Also if I don't do edge detection in the sync circuit but use the
following piece of code in my block will it work and synthesize? (just
curious)

if (pCLK = '1 and pCLK'event) then
-- assume synchronizer is only 2 stage
-- and no edge detection is done in synchronizer
-- detect edge here
if (NEWLINE_p = '1' and NEWLINE_P'event) then

...

end if;

I have never seen 'event being used anywhere except for the clk which
is why I am asking this.

Thanks,
Divyang M

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:[email protected]
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

 

[Jim Lewis]

Neo,
I would not recommend using the stage1fifo for anything.
It is intended for metastable resolution.

If you need glitch suppression, you may need additional
registers in the term like you suggested. When crossing
clock domains, I would not expect need to do this. The
control signal crossing the clock domain needs to come
directly from the output of a register of the other clock
and directly into the registers of this clock domain.

Cheers,
Jim

divyang,
You are just checking for the rising edge of the data but not the
duration. so your output will always be one clock cycle in faster
domain even if the data remains high for multiple clock cycles in the
slower domain. This modification should check for that:
if ((stage2fifo = '1' and pulsefifo = '0') or stage1fifo = '1') then
---

--
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training mailto:[email protected]
SynthWorks Design Inc. http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~