library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY pwm1 IS
PORT(
clk : IN std_logic;
connect : buffer std_logic;
pwm_in : in std_logic_vector(4 downto 0);
pwm_out : out std_logic);
END pwm1;
architecture behavorial of pwm1 is
signal clk1: std_logic;
signal count: std_logic_vector (4 downto 0) := "00000";
BEGIN
divisor: process (clk)
variable resolution : integer:=0;
constant resolution_limit : integer := 32;
variable divider : integer:=0;
constant divider_limit : integer :=1000;
begin
if (clk'EVENT AND clk='1') then
if divider = divider_limit then
divider := 0;
Clk1 <= '1';
else
divider := divider + 1;
Clk1 <= '0';
end if;
if resolution = resolution_limit then
resolution := 0;
connect <= '1';
else
resolution := resolution + 1;
connect <= '0';
end if;
end if;
end process divisor;
pwm: process (Clk, connect)
begin
if connect ='1' then
count <= "00000";
elsif clk'event and clk ='1' then
if Clk1='1' then
count <= count + '1';
if count < pwm_in then
pwm_out <= '1';
else
pwm_out <= '0';
end if;
end if;
end if;
end process pwm;
END behavorial
Want to reply to this thread or ask your own question?
You'll need to choose a username for the site, which only take a couple of moments. After that, you can post your question and our members will help you out.