Port "arg" is not constrained?

[cltsaig]

Hi all,

Can someone help me out to overwhelm this problem? The error message "arg
port is not constrained" was occured during the starting of simulation
when I assigned a test waveform.
Technically, Alan (www.doulos.com) had suggested me to implement this
function by using a procedure rather than declared as an entity, this will
get away of this problem. However, I don't know to write a procedure with
clock input. May someone provide me some suggestion to solve this problem
please? Thanks for reading this post!!!


Sincerely,
Stanley

------------------------- my VHDL code here -------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.fphdl_base_pkg.all;
use work.fphdl32_pkg.all;


-- type array_fp32 is array (natural range <>) of fp32;
-- type array_integer is array (natural range <>) of integer;

entity TEST is
port(
arg: in array_fp32 ;
nn: in array_integer;
ndim: in integer;
isign: in integer;
clk:in std_logic;
rst:in std_logic;
resultut array_fp32
);
end TEST;


architecture computation of TEST is


subtype size_array_fp32 is array_fp32(1 to 10);
signal temp_in: size_array_fp32;


begin

feed_arg: process (clk, rst) is
begin
if rst = '0' then
elsif rising_edge(clk) then
temp_in<=arg;
end if;
end process feed_arg;
-------------------------------------

-- process to evaluate ntot, nprev
MAIN: process (clk, rst) is
variable ntot, nprev, n, nrem: integer;
variable i1, i2, i3, ip1, ip2, ip3, i2rev, i3rev: integer;
variable temp_a, temp_b: fp32;

------- Procedure -----------
-- #define SWAP(a,b) tempr=(a);(a)=(b);(b)=tempr
procedure SWAP(
a:inout fp32;
b:inout fp32
) is
variable tempr:fp32;
begin
tempr:=a;
a:=b;
b:=tempr;
end SWAP;


begin
if rst='0' then

elsif rising_edge(clk) then

for idim in 1 to ndim loop
ntot := ntot * nn(idim);
nprev:=1;
for idim in ndim downto 1 loop
n:=nn(idim);
nrem:=ntot/(n*nprev);
ip1:=to_integer(to_unsigned(nprev,32) sll 1);
ip2:=ip1*n;
ip3:=ip2*nrem;
i2rev:=1;
i2:=1;
while i2 < ip2 loop
if i2<i2rev then
i1:=i2;
while i1 <= i2+ip1-2 loop
i3:=i1;
while i3 <= ip3 loop
i3rev:=i2rev+i3-i2;
-- SWAP(data[i3],data[i3rev]);
--temp_a:=arg(i3);
--temp_b:=arg(i3rev);
-- SWAP(temp_in(i3),temp_in(i3rev));
-- SWAP(data[i3+1],data[i3rev+1]);
i3:=i3+ip2;
end loop;
i1:=i1+2;
end loop;
end if;
i2:=i2+ip1;
end loop;
end loop;
end loop;
end if;
end process MAIN;
end architecture;
------------------------- my VHDL code end ---------------


------------------------- C code ---------------------------
#define SWAP(a,b) tempr=(a);(a)=(b);(b)=tempr
void test(float data[], unsigned long nn[], int ndim)
{
int idim;
unsigned long i1,i2,i3,i2rev,i3rev,ip1,ip2,ip3;
unsigned long k1,k2,n,nprev,nrem,ntot;

for (ntot=1,idim=1;idim<=ndim;idim++)
ntot *= nn[idim];
nprev=1;
for (idim=ndim;idim>=1;idim--) {
n=nn[idim];
nrem=ntot/(n*nprev);
ip1=nprev << 1;
ip2=ip1*n;
ip3=ip2*nrem;
i2rev=1;
for (i2=1;i2<=ip2;i2+=ip1) {
if (i2 < i2rev) {
for (i1=i2;i1<=i2+ip1-2;i1+=2) {
for (i3=i1;i3<=ip3;i3+=ip2) {
i3rev=i2rev+i3-i2;
SWAP(data[i3],data[i3rev]);
SWAP(data[i3+1],data[i3rev+1]);
}
}
}
}
}
}
------------------------ C code end ------------------------

 

[Egbert Molenkamp]

Before you can simulate you have to constrain the unconstrained arrays.
In your entity TEST you have three unconstrained arrays that are not
unconstrained if this entity is the top level:

arg: in array_fp32 ;
nn: in array_integer;
resultut array_fp32

You could add a generic part to constrain these I/Os, something like:

entity test is
generic (lgt_int : integer:=4; lgt_fp32 : integer := 5);
port (arg: in array_fp32(lgt_fp32-1 downto 0) ;
nn: in array_integer(lgt_int-1 downto 0);
resultut array_fp32(lgt_fp32-1 downto 0);
.....

If this entity is used in another design you simply can add a "generic map"
where is entity is instantiated to change the generic values in the entity.

Egbert Molenkamp

Hi all,

Can someone help me out to overwhelm this problem? The error message "arg
port is not constrained" was occured during the starting of simulation
when I assigned a test waveform.
Technically, Alan (www.doulos.com) had suggested me to implement this
function by using a procedure rather than declared as an entity, this will
get away of this problem. However, I don't know to write a procedure with
clock input. May someone provide me some suggestion to solve this problem
please? Thanks for reading this post!!!


Sincerely,
Stanley

------------------------- my VHDL code here -------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.fphdl_base_pkg.all;
use work.fphdl32_pkg.all;


-- type array_fp32 is array (natural range <>) of fp32;
-- type array_integer is array (natural range <>) of integer;

entity TEST is
port(
arg: in array_fp32 ;
nn: in array_integer;
ndim: in integer;
isign: in integer;
clk:in std_logic;
rst:in std_logic;
resultut array_fp32
);
end TEST;


architecture computation of TEST is


subtype size_array_fp32 is array_fp32(1 to 10);
signal temp_in: size_array_fp32;


begin

feed_arg: process (clk, rst) is
begin
if rst = '0' then
elsif rising_edge(clk) then
temp_in<=arg;
end if;
end process feed_arg;
-------------------------------------

-- process to evaluate ntot, nprev
MAIN: process (clk, rst) is
variable ntot, nprev, n, nrem: integer;
variable i1, i2, i3, ip1, ip2, ip3, i2rev, i3rev: integer;
variable temp_a, temp_b: fp32;

------- Procedure -----------
-- #define SWAP(a,b) tempr=(a);(a)=(b);(b)=tempr
procedure SWAP(
a:inout fp32;
b:inout fp32
) is
variable tempr:fp32;
begin
tempr:=a;
a:=b;
b:=tempr;
end SWAP;


begin
if rst='0' then

elsif rising_edge(clk) then

for idim in 1 to ndim loop
ntot := ntot * nn(idim);
nprev:=1;
for idim in ndim downto 1 loop
n:=nn(idim);
nrem:=ntot/(n*nprev);
ip1:=to_integer(to_unsigned(nprev,32) sll 1);
ip2:=ip1*n;
ip3:=ip2*nrem;
i2rev:=1;
i2:=1;
while i2 < ip2 loop
if i2<i2rev then
i1:=i2;
while i1 <= i2+ip1-2 loop
i3:=i1;
while i3 <= ip3 loop
i3rev:=i2rev+i3-i2;
-- SWAP(data[i3],data[i3rev]);
--temp_a:=arg(i3);
--temp_b:=arg(i3rev);
-- SWAP(temp_in(i3),temp_in(i3rev));
-- SWAP(data[i3+1],data[i3rev+1]);
i3:=i3+ip2;
end loop;
i1:=i1+2;
end loop;
end if;
i2:=i2+ip1;
end loop;
end loop;
end loop;
end if;
end process MAIN;
end architecture;
------------------------- my VHDL code end ---------------


------------------------- C code ---------------------------
#define SWAP(a,b) tempr=(a);(a)=(b);(b)=tempr
void test(float data[], unsigned long nn[], int ndim)
{
int idim;
unsigned long i1,i2,i3,i2rev,i3rev,ip1,ip2,ip3;
unsigned long k1,k2,n,nprev,nrem,ntot;

for (ntot=1,idim=1;idim<=ndim;idim++)
ntot *= nn[idim];
nprev=1;
for (idim=ndim;idim>=1;idim--) {
n=nn[idim];
nrem=ntot/(n*nprev);
ip1=nprev << 1;
ip2=ip1*n;
ip3=ip2*nrem;
i2rev=1;
for (i2=1;i2<=ip2;i2+=ip1) {
if (i2 < i2rev) {
for (i1=i2;i1<=i2+ip1-2;i1+=2) {
for (i3=i1;i3<=ip3;i3+=ip2) {
i3rev=i2rev+i3-i2;
SWAP(data[i3],data[i3rev]);
SWAP(data[i3+1],data[i3rev+1]);
}
}
}
}
}
}
------------------------ C code end ------------------------

 

[cltsaig]

Hi Egbert,

Thanks for your feedback, I'll adopt your approach and update you the
result sooner!

Stanley