J
john
Hello,
I am trying to do write the data into the RAm using CPLD..
CPLD is interfaced to a USB chip wjich is producing new
data at each falling edge of the clock. Now, My question
is that I am directing equating the USB bus( 8 bit port )
to the data bus . Is it right way to do it?
Thanks
John
Entity DPR is
port (
Data_Bus : out unsigned (13 downto 0);
USB_Data :in unsigned ( 7 downto 0);
);
End DPR;
Process( State2 )
Begin
Case State2 is
When G0=>
inc <='1';
Data_Bus ( 13 downto 8) <= USB_Data ( 5 downto 0 );
UBL <='0'; --1 old value
LBL <='1'; --0 0ld value
nextstate2 <=G1;
When G1 =>
inc <='0';
Data_Bus ( 7 downto 0) <= USB_Data ( 7 downto 0 );
UBL <='1'; --0 old value
LBL <='0'; --1 old value
nextstate2 <=G0;
When others =>
nextstate2 <=G0;
End case;
End Process;
Process (USB_CLK )
Begin
If( USB_CLK 'Event And USB_CLK ='0' ) Then
State2 <= nextstate2;
State <= nextstate;
End If;
End Process;
End DPR_ARCH;
I am trying to do write the data into the RAm using CPLD..
CPLD is interfaced to a USB chip wjich is producing new
data at each falling edge of the clock. Now, My question
is that I am directing equating the USB bus( 8 bit port )
to the data bus . Is it right way to do it?
Thanks
John
Entity DPR is
port (
Data_Bus : out unsigned (13 downto 0);
USB_Data :in unsigned ( 7 downto 0);
);
End DPR;
Process( State2 )
Begin
Case State2 is
When G0=>
inc <='1';
Data_Bus ( 13 downto 8) <= USB_Data ( 5 downto 0 );
UBL <='0'; --1 old value
LBL <='1'; --0 0ld value
nextstate2 <=G1;
When G1 =>
inc <='0';
Data_Bus ( 7 downto 0) <= USB_Data ( 7 downto 0 );
UBL <='1'; --0 old value
LBL <='0'; --1 old value
nextstate2 <=G0;
When others =>
nextstate2 <=G0;
End case;
End Process;
Process (USB_CLK )
Begin
If( USB_CLK 'Event And USB_CLK ='0' ) Then
State2 <= nextstate2;
State <= nextstate;
End If;
End Process;
End DPR_ARCH;