A
ashu
hi
my code given below is taking too much of (600) logic cells t& max
opreating freq is 7 MHZ i think which is very less,
can u plz suggest me some remedy........
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
entity test is
port ( clk,sta_in : in std_logic ;
sta_out : out std_logic ;
sel : in bit_vector ( 2 downto 0 ) ;
data_in : in integer range -2047 to 2047 ;
data_out : out integer range -127 to 127 );
end test ;
architecture a of test is
begin
process( clk,sta_in )
variable mul : integer range -65535 to 65535 ;
variable mul1 : integer range -127 to 127 ;
variable s : std_logic_vector(0 to 16 ) ;
variable b,b1 : bit_vector ( 0 to 16 ) ;
variable b2 : bit_vector ( 0 to 7 ) ;
variable s2 : std_logic_vector ( 0 to 7 ) ;
begin
if ( clk 'event and clk = '1' ) then
if ( sta_in = '1' ) then
mul := 32 * data_in ;
case sel is
when "000" =>
mul := mul ;
when "001" =>
mul := mul / 5 ;
mul := mul * 4 ;
when "010" =>
mul := mul / 5 ;
mul := mul * 3 ;
when "011" =>
mul := mul / 2 ;
when "100" =>
mul := mul / 5 ;
mul := mul * 2 ;
when "101" =>
mul := mul / 5 ;
when "110" =>
mul := mul / 10 ;
when "111" =>
mul := mul / 20 ;
end case ;
s := conv_std_logic_vector( mul ,17 ) ;
b := to_bitvector(s) ;
b1 := b srl 9 ;
s := to_stdlogicvector( b1 ) ;
mul1 := conv_integer ( signed(s) ) ;
if ( b (8)= '1' ) then
mul1 := mul1 + 1 ;
else
mul1 := mul1 ;
end if ;
dat_out <= mul1 ;
sta_out <= sta_in ;
else
sta_out <= '0' ;
end if ;
end if ;
end process ;
end a ;
code is working logically its is producing the required outputs but
timing analyzer tool is showing max delay of 130ns due to which max
freq is limited to 7 mhz
should i try some other conversion functions etc.......plz let me know
about that
ashwani anand
my code given below is taking too much of (600) logic cells t& max
opreating freq is 7 MHZ i think which is very less,
can u plz suggest me some remedy........
library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
entity test is
port ( clk,sta_in : in std_logic ;
sta_out : out std_logic ;
sel : in bit_vector ( 2 downto 0 ) ;
data_in : in integer range -2047 to 2047 ;
data_out : out integer range -127 to 127 );
end test ;
architecture a of test is
begin
process( clk,sta_in )
variable mul : integer range -65535 to 65535 ;
variable mul1 : integer range -127 to 127 ;
variable s : std_logic_vector(0 to 16 ) ;
variable b,b1 : bit_vector ( 0 to 16 ) ;
variable b2 : bit_vector ( 0 to 7 ) ;
variable s2 : std_logic_vector ( 0 to 7 ) ;
begin
if ( clk 'event and clk = '1' ) then
if ( sta_in = '1' ) then
mul := 32 * data_in ;
case sel is
when "000" =>
mul := mul ;
when "001" =>
mul := mul / 5 ;
mul := mul * 4 ;
when "010" =>
mul := mul / 5 ;
mul := mul * 3 ;
when "011" =>
mul := mul / 2 ;
when "100" =>
mul := mul / 5 ;
mul := mul * 2 ;
when "101" =>
mul := mul / 5 ;
when "110" =>
mul := mul / 10 ;
when "111" =>
mul := mul / 20 ;
end case ;
s := conv_std_logic_vector( mul ,17 ) ;
b := to_bitvector(s) ;
b1 := b srl 9 ;
s := to_stdlogicvector( b1 ) ;
mul1 := conv_integer ( signed(s) ) ;
if ( b (8)= '1' ) then
mul1 := mul1 + 1 ;
else
mul1 := mul1 ;
end if ;
dat_out <= mul1 ;
sta_out <= sta_in ;
else
sta_out <= '0' ;
end if ;
end if ;
end process ;
end a ;
code is working logically its is producing the required outputs but
timing analyzer tool is showing max delay of 130ns due to which max
freq is limited to 7 mhz
should i try some other conversion functions etc.......plz let me know
about that
ashwani anand