My code:
Integer is an Integer Variable
OutputNumber is an Std_logic_Vector Input
Integer <= conv_integer(OutputNumber);
MyVector(37 downto (38-Integer)) <= Temp(37 downto (38-Integer));
Compiler Error:
Error (10454): VHDL syntax error: right bound of range must be a constant
PLEASE HELP ME.
Integer is an Integer Variable
OutputNumber is an Std_logic_Vector Input
Integer <= conv_integer(OutputNumber);
MyVector(37 downto (38-Integer)) <= Temp(37 downto (38-Integer));
Compiler Error:
Error (10454): VHDL syntax error: right bound of range must be a constant
PLEASE HELP ME.
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