Problem with timing in post PAR with Xilinx Virtex II

[Steven]

Hi, all

I have timing violation with a sdram controller design. The function ,
post map simulation works fine( except some initialise timing
violation, I think I can ignore it, right ? ).

My target platform is virtex II 250. Input clock 25Mhz is doubled with
mirrored DCMs to get internal and external 50MHz. External 50Mhz goes
to drive MICRON sdram 256Mb ( mt48lc16m16a2 ). The internal 50Mhz and
ext 50Mhz are not aligned perfectly, some delay is there.

In post par simulation, I got "X" with 2 bits on data bus, but not on
whole write data cycles . The micron sim module reports timing
violation here and there.

I doubt many timing violation from micron module can be ignored,
because when I simulates xapp134, there are endless timing violations,
but xilinx says the design is validated.

The hardware test shows several bits can be read after write, but the
bits after X are wrong. I have not imposed UCF constraints yet.

My question is how can I get rid of these "X" ? Can the delay between
int/ext clk be got rid of or it is not important. How about the
Setup/Hold timing violation reported by micron module ?

I have put the wave output and text output at, please have a look.

http://mitglied.lycos.de/dxslyz/fourphotogalery.html

please excuse me not know how to post the link to be click friendly.

Thanks in advance for any suggestions.

Steven Yu.



Following is the text output from modelsim.

# tb_1.micron256 : at time 1318.0 ns AREF : Auto Refresh
# tb_1.micron256 : at time 1478.0 ns LMR : Load Mode Register
# tb_1.micron256 : CAS Latency = 2
# tb_1.micron256 : Burst Length = 8
# tb_1.micron256 : Burst Type = Sequential
# tb_1.micron256 : Write Burst Mode = Programmed Burst
Length

# ** Error: mt48lc16m16a2.v(1068): $setup( Addr:1476746 ps, posedge
Clk:1477957 ps, 1500 ps );
# Time: 1477957 ps Iteration: 1 Instance: /tb_1/micron256
---------------problem ------------------------
# ** Error: mt48lc16m16a2.v(1068): $setup( Addr:1496746 ps, posedge
Clk:1497957 ps, 1500 ps );
# Time: 1497957 ps Iteration: 1 Instance: /tb_1/micron256
---------------problem ------------------------

# tb_1.micron256 : at time 1518.0 ns AREF : Auto Refresh
# ** Note: ### write ###
# Time: 2 us Iteration: 0 Instance: /tb_1
# tb_1.micron256 : at time 2058.0 ns ACT : Bank = 0 Row = 0
# tb_1.micron256 : at time 2158.0 ns WRITE: Bank = 0 Row =0, Col
=0, Data =3
# tb_1.micron256 : at time 2178.0 ns WRITE: Bank = 0 Row =0, Col
=1, Data =4
# tb_1.micron256 : at time 2198.0 ns WRITE: Bank = 0 Row =0, Col
=2, Data =5
# tb_1.micron256 : at time 2218.0 ns WRITE: Bank = 0 Row =0, Col
=3, Data =6
# tb_1.micron256 : at time 2238.0 ns WRITE: Bank = 0 Row =0, Col
=4, Data =7

# ** Warning: /X_LATCHE SETUP High VIOLATION ON I WITH RESPECT TO CLK;
# Expected := 0.182 ns; Observed := 0.004 ns; At : 2251.933 ns
# Time: 2251933 ps Iteration: 5 Instance:
/tb_1/uut/uut/data_sys_in_4
---------------problem ------------------------

# ** Warning: /X_LATCHE SETUP High VIOLATION ON I WITH RESPECT TO CLK;
# Expected := 0.182 ns; Observed := 0.004 ns; At : 2251.933 ns
# Time: 2251933 ps Iteration: 5 Instance:
/tb_1/uut/uut/data_sys_in_6
---------------problem ------------------------

# tb_1.micron256 : at time 2258.0 ns WRITE: Bank = 0 Row = 0, Col
=5, Data =X
---------------problem ------------------------

# tb_1.micron256 : at time 2278.0 ns WRITE: Bank = 0 Row = 0, Col
=6, Data =1

# ** Warning: /X_LATCHE SETUP High VIOLATION ON I WITH RESPECT TO CLK;
# Expected := 0.182 ns; Observed := 0.004 ns; At : 2291.933 ns
# Time: 2291933 ps Iteration: 5 Instance:
/tb_1/uut/uut/data_sys_in_4
# ** Warning: /X_LATCHE SETUP High VIOLATION ON I WITH RESPECT TO CLK;
# Expected := 0.182 ns; Observed := 0.004 ns; At : 2291.933 ns
# Time: 2291933 ps Iteration: 5 Instance:
/tb_1/uut/uut/data_sys_in_6
---------------problem ------------------------

# tb_1.micron256 : at time 2298.0 ns WRITE: Bank = 0 Row =0, Col =7,
Data =X
---------------problem ------------------------


# tb_1.micron256 : at time 2318.0 ns NOTE : Start Internal Auto
Precharge for Bank 0
# tb_1.micron256 : at time 17338.0 ns AREF : Auto Refresh
# ** Note: ### Read ###
# Time: 23120 ns Iteration: 0 Instance: /tb_1
# tb_1.micron256 : at time 23178.0 ns ACT : Bank = 0 Row = 0
# tb_1.micron256 : at time 23303.0 ns READ : Bank = 0 Row = 0, Col =
0, Data = 3
# tb_1.micron256 : at time 23323.0 ns READ : Bank = 0 Row = 0, Col =
1, Data = 4
# tb_1.micron256 : at time 23343.0 ns READ : Bank = 0 Row = 0, Col =
2, Data = 5
# tb_1.micron256 : at time 23363.0 ns READ : Bank = 0 Row = 0, Col =
3, Data = 6
# tb_1.micron256 : at time 23383.0 ns READ : Bank = 0 Row = 0, Col =
4, Data = 7
---------------problem ------------------------
# tb_1.micron256 : at time 23403.0 ns READ : Bank = 0 Row = 0, Col =
5, Data = X

# tb_1.micron256 : at time 23423.0 ns READ : Bank = 0 Row = 0, Col =
6, Data = 1