Since I have 36 bit addresses, I now have to do more work to get them out..
You're statement that an unsigned can deal with greater than 31 bits is unfounded for VHDL in general. There's also not an arithmetic operator defined for std_logic_vector by default in VHDL unless you're also using synopsys's package std_logic_unsigned. You should consider it anathema to mix numeric_std (which provides unsigned) with synopsys's packages.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test is
end entity;
architecture foo of test is
function unsigned_to_string (inp: unsigned) return string is
variable tmp: string (1 to inp'LENGTH) := "";
variable eval: character;
variable index: positive;
begin
for i in inp'RANGE loop
if inp(i) = 'U' then eval := 'U';
elsif inp(i) = 'X' then eval := 'X';
elsif inp(i) = '0' then eval := '0';
elsif inp(i) = '1' then eval := '1';
elsif inp(i) = 'Z' then eval := 'Z';
elsif inp(i) = 'W' then eval := 'W';
elsif inp(i) = 'L' then eval := 'L';
elsif inp(i) = 'H' then eval := 'H';
else eval := '-';
end if ;
tmp(index) := eval;
index := index + 1;
end loop;
return tmp;
end function;
signal A: unsigned (31 downto 0);
signal B: unsigned (35 downto 0);
signal C: unsigned (35 downto 0);
begin
A <= x"80000000" after 1 ns;
B <= x"800000000" after 1 ns;
C <= A + B;
MONITOR:
assert C = x"FFFFFFFFF"
report LF & "A = " & unsigned_to_string(A) & LF &
"B = " & unsigned_to_string(B) & LF &
"C = " & unsigned_to_string(C)
severity NOTE;
end architecture;
%% ghdl -a unsigned.vhdl
%% ghdl -e test
%% ghdl -r test
.../../../src/ieee/numeric_std-body.v93:1613:7
0ms
assertion warning): NUMERIC_STD."=": metavalue detected, returning FALSE
unsigned.vhdl:40:1
0ms
assertion note):
A = UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU
B = UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU
C = UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU
.../../../src/ieee/numeric_std-body.v93:1613:7
0ms
assertion warning): NUMERIC_STD."=": metavalue detected, returning FALSE
unsigned.vhdl:40:1
0ms
assertion note):
A = UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU
B = UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU
C = XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
unsigned.vhdl:40:1
1ns
assertion note):
A = 10000000000000000000000000000000
B = 100000000000000000000000000000000000
C = 100010000000000000000000000000000000
%%
All the 'U's are expected from the default assignment to the left most value of std_ulogic for each element of the unsigned arrays. The second reportis due to no delay in the assignment of C. You get all 'X's adding two arrays of 'U's. The third report shows the results of C <= A + B;
unsigned is an array of std_logic which uses a nine value representation todescribe bit values ('U','X','0','1','Z','W','L','H','-'). The function "+" (an adding operator) is defined in package numeric_std.
You could note I was too lazy to convert unsigned to string representationsin base 16, they are shown by std_logic element (i.e. bit by bit).
There's also useful information derived from familiarity with the packages,for example the array length of the result for the function "+" (an operator) is derived from the MAX of the length of it's two arguments. C is a anarray of the std_ulogic nine level (MVL9 originally from Synopsys) representation of an array of bits that has a range of 35 downto 0 (36 bits).
Perhaps you could show us an example VHDL description that exhibits your problem?
