Hi,
I've encountered an odd problem going from synthesis to routing. I am aware that it would be very difficult pinpointing what my problem might be, but I thought I'd air it with you guys, to see if maybe this problem has occured to others. Or if not, perhaps someone has some general pointers to what I could look for when debugging my problem (I'm very new to VHDL design for FPGAs).
My design can be simplified to the following: It is driven by an external 32MHz clock, which is divided down to a 10kHz clock, which runs the rest of the circuit. When a counter reaches a certain value (which is hard-coded), it generates a trigger signal as the output.
The behavioural simulation (in ModelSim) works with no problems. However, after I synthesize the design and map it to my FPGA evaluation board (SiliconBlue), the trigger signal is activated approximately twice as fast as it should. One might think that I did the clock division wrong, but my post-synthesis simulation works as it should. However, when I do the post-routing simulation, the trigger signal is activated according to what I observe from the evaluation board. So something is happening from the synthesis to the routing. The static timing report gives no negative slack.
I'd appreciate any kinds of input.
Thanks!
I've encountered an odd problem going from synthesis to routing. I am aware that it would be very difficult pinpointing what my problem might be, but I thought I'd air it with you guys, to see if maybe this problem has occured to others. Or if not, perhaps someone has some general pointers to what I could look for when debugging my problem (I'm very new to VHDL design for FPGAs).
My design can be simplified to the following: It is driven by an external 32MHz clock, which is divided down to a 10kHz clock, which runs the rest of the circuit. When a counter reaches a certain value (which is hard-coded), it generates a trigger signal as the output.
The behavioural simulation (in ModelSim) works with no problems. However, after I synthesize the design and map it to my FPGA evaluation board (SiliconBlue), the trigger signal is activated approximately twice as fast as it should. One might think that I did the clock division wrong, but my post-synthesis simulation works as it should. However, when I do the post-routing simulation, the trigger signal is activated according to what I observe from the evaluation board. So something is happening from the synthesis to the routing. The static timing report gives no negative slack.
I'd appreciate any kinds of input.
Thanks!