Problems with file input

[SR]

Hello,

I am trying to simulate a 16-bit shift register using the following
program:

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use std.textio.all;

entity ShiftReg is
Port (d_in : in std_logic_vector(15 downto 0);
serial_in,ld,shift,clk,reset : in std_logic;
q : inout std_logic_vector(15 downto 0));
end entity ShiftReg;

architecture behavioral of ShiftReg is
subtype word is std_logic_vector(15 downto 0);
type initz is file of word;
begin
P: process (clk, shift, ld,reset)
file datain : initz open read_mode is
"C:/Modeltech_xe_starter/examples/ch 10/init.txt";
variable val : word;

begin
if (reset='1') then
while not(endfile(datain)) loop
read(datain,val);
end loop;
elsif ( clk'event and clk ='1') then
if (shift = '0') and (ld='1') then
q <= d_in ;
elsif (shift = '1') then
q(14 downto 0) <= q(15 downto 1) ;
q(15) <= serial_in ;
end if;
end if;
end process P;
end architecture behavioral;

The file init.txt just contains the string 1110000000000001

And the simulation settings that I used where

force clk '0' 1 ns, '1' 2 ns -repeat 2 ns
force reset '1','0' 3 ns
force ld '0'
force d_in '0000111100001111'
force shift '0'
force serial_in '0'

What happens is that the variable val remains undefined and as a result
q always remains undefined.If someone can help me with as to why this
program does not read in from the file, I would be much obliged.

Thanks, and I appreciate the consideration.

Mani

 

[Egbert Molenkamp]

I assume the initialization file is a text file.
Have a look at (and following chapters)
http://www.vhdl.org/vi/comp.lang.vhdl/FAQ1.html#files

I added a corrected version (see --**)

architecture behavioral of ShiftReg is
subtype word is std_logic_vector(15 downto 0);
begin
P: process (clk, shift, ld,reset)
file datain : TEXT open read_mode is
"C:/Modeltech_xe_starter/examples/ch 10/init.txt";
variable d : bit_vector(15 DOWNTO 0); --**
variable L : line; --**
begin
if (reset='1') then
while not(endfile(datain)) loop
readline(datain,L); --**
read(L,d); --**
q <= to_stdlogicvector(d); --**
end loop;
elsif ( clk'event and clk ='1') then
if (shift = '0') and (ld='1') then
q <= d_in ;
elsif (shift = '1') then
q(14 downto 0) <= q(15 downto 1) ;
q(15) <= serial_in ;
-- alternative for previous two lines is: q <= serial_in & q (15
downto 1);
end if;
end if;
end process P;
end architecture behavioral;

Egbert Molenkamp

 

[SR]

Thanks for helping me out Egbert. I appreciate it.

Mani